diff options
author | Richard Zhao <rizhao@nvidia.com> | 2015-07-23 18:10:42 -0400 |
---|---|---|
committer | Richard Zhao <rizhao@nvidia.com> | 2015-08-19 08:12:00 -0400 |
commit | a88e58cc9d2c4b9f852716240b3cabc9449d8679 (patch) | |
tree | 5965b2645913695ed36e61aa4c42fdb60045cf42 /drivers/gpu/nvgpu/vgpu | |
parent | db8bce518bcf2a1b46e5897f55469f348a16c9a2 (diff) |
gpu: nvgpu: vgpu: add t210 gm20b support
- add hal initializaiton
- create folders vgpu/gk20a and vgpu/gm20b for specific code
Bug 1653185
Change-Id: If94d45e22a1d73d2e4916673736cc29751be4e40
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/774148
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-by: Ken Adams <kadams@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gk20a/vgpu_gr_gk20a.c | 50 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gk20a/vgpu_gr_gk20a.h | 21 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gk20a/vgpu_hal_gk20a.c | 29 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.c | 42 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.h | 21 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c | 29 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gr_vgpu.c | 68 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/ltc_vgpu.c | 36 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/mm_vgpu.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/vgpu.c | 31 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/vgpu.h | 4 |
11 files changed, 295 insertions, 37 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gk20a/vgpu_gr_gk20a.c b/drivers/gpu/nvgpu/vgpu/gk20a/vgpu_gr_gk20a.c new file mode 100644 index 00000000..8d32773e --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gk20a/vgpu_gr_gk20a.c | |||
@@ -0,0 +1,50 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | |||
16 | #include "gk20a/hw_gr_gk20a.h" | ||
17 | #include "gk20a/gk20a.h" | ||
18 | #include "vgpu/vgpu.h" | ||
19 | |||
20 | static void vgpu_gk20a_detect_sm_arch(struct gk20a *g) | ||
21 | { | ||
22 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); | ||
23 | u32 v = 0, raw_version, version = 0; | ||
24 | |||
25 | gk20a_dbg_fn(""); | ||
26 | |||
27 | if (vgpu_get_attribute(platform->virt_handle, | ||
28 | TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH, &v)) | ||
29 | gk20a_err(dev_from_gk20a(g), "failed to retrieve SM arch"); | ||
30 | |||
31 | raw_version = gr_gpc0_tpc0_sm_arch_spa_version_v(v); | ||
32 | |||
33 | if (raw_version == gr_gpc0_tpc0_sm_arch_spa_version_smkepler_lp_v()) | ||
34 | version = 0x320; /* SM 3.2 */ | ||
35 | else | ||
36 | gk20a_err(dev_from_gk20a(g), "Unknown SM version 0x%x", | ||
37 | raw_version); | ||
38 | |||
39 | /* on Kepler, SM version == SPA version */ | ||
40 | g->gpu_characteristics.sm_arch_spa_version = version; | ||
41 | g->gpu_characteristics.sm_arch_sm_version = version; | ||
42 | |||
43 | g->gpu_characteristics.sm_arch_warp_count = | ||
44 | gr_gpc0_tpc0_sm_arch_warp_count_v(v); | ||
45 | } | ||
46 | |||
47 | void vgpu_gk20a_init_gr_ops(struct gpu_ops *gops) | ||
48 | { | ||
49 | gops->gr.detect_sm_arch = vgpu_gk20a_detect_sm_arch; | ||
50 | } | ||
diff --git a/drivers/gpu/nvgpu/vgpu/gk20a/vgpu_gr_gk20a.h b/drivers/gpu/nvgpu/vgpu/gk20a/vgpu_gr_gk20a.h new file mode 100644 index 00000000..bb80aff8 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gk20a/vgpu_gr_gk20a.h | |||
@@ -0,0 +1,21 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #ifndef __VGPU_GR_GK20A_H__ | ||
15 | #define __VGPU_GR_GK20A_H__ | ||
16 | |||
17 | #include "gk20a/gk20a.h" | ||
18 | |||
19 | void vgpu_gk20a_init_gr_ops(struct gpu_ops *gops); | ||
20 | |||
21 | #endif | ||
diff --git a/drivers/gpu/nvgpu/vgpu/gk20a/vgpu_hal_gk20a.c b/drivers/gpu/nvgpu/vgpu/gk20a/vgpu_hal_gk20a.c new file mode 100644 index 00000000..aeeb2ad9 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gk20a/vgpu_hal_gk20a.c | |||
@@ -0,0 +1,29 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #include "gk20a/hal_gk20a.h" | ||
15 | #include "vgpu/vgpu.h" | ||
16 | #include "vgpu_gr_gk20a.h" | ||
17 | |||
18 | int vgpu_gk20a_init_hal(struct gk20a *g) | ||
19 | { | ||
20 | int err; | ||
21 | |||
22 | err = gk20a_init_hal(g); | ||
23 | if (err) | ||
24 | return err; | ||
25 | vgpu_init_hal_common(g); | ||
26 | vgpu_gk20a_init_gr_ops(&g->ops); | ||
27 | |||
28 | return 0; | ||
29 | } | ||
diff --git a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.c b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.c new file mode 100644 index 00000000..0ebecfe4 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.c | |||
@@ -0,0 +1,42 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | |||
16 | #include "gm20b/hw_gr_gm20b.h" | ||
17 | #include "gk20a/gk20a.h" | ||
18 | #include "vgpu/vgpu.h" | ||
19 | |||
20 | static void vgpu_gm20b_detect_sm_arch(struct gk20a *g) | ||
21 | { | ||
22 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); | ||
23 | u32 v = 0; | ||
24 | |||
25 | gk20a_dbg_fn(""); | ||
26 | |||
27 | if (vgpu_get_attribute(platform->virt_handle, | ||
28 | TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH, &v)) | ||
29 | gk20a_err(dev_from_gk20a(g), "failed to retrieve SM arch"); | ||
30 | |||
31 | g->gpu_characteristics.sm_arch_spa_version = | ||
32 | gr_gpc0_tpc0_sm_arch_spa_version_v(v); | ||
33 | g->gpu_characteristics.sm_arch_sm_version = | ||
34 | gr_gpc0_tpc0_sm_arch_sm_version_v(v); | ||
35 | g->gpu_characteristics.sm_arch_warp_count = | ||
36 | gr_gpc0_tpc0_sm_arch_warp_count_v(v); | ||
37 | } | ||
38 | |||
39 | void vgpu_gm20b_init_gr_ops(struct gpu_ops *gops) | ||
40 | { | ||
41 | gops->gr.detect_sm_arch = vgpu_gm20b_detect_sm_arch; | ||
42 | } | ||
diff --git a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.h b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.h new file mode 100644 index 00000000..75dfebf7 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.h | |||
@@ -0,0 +1,21 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #ifndef __VGPU_GR_GM20B_H__ | ||
15 | #define __VGPU_GR_GM20B_H__ | ||
16 | |||
17 | #include "gk20a/gk20a.h" | ||
18 | |||
19 | void vgpu_gm20b_init_gr_ops(struct gpu_ops *gops); | ||
20 | |||
21 | #endif | ||
diff --git a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c new file mode 100644 index 00000000..c9cb0ade --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c | |||
@@ -0,0 +1,29 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #include "gm20b/hal_gm20b.h" | ||
15 | #include "vgpu/vgpu.h" | ||
16 | #include "vgpu_gr_gm20b.h" | ||
17 | |||
18 | int vgpu_gm20b_init_hal(struct gk20a *g) | ||
19 | { | ||
20 | int err; | ||
21 | |||
22 | err = gm20b_init_hal(g); | ||
23 | if (err) | ||
24 | return err; | ||
25 | vgpu_init_hal_common(g); | ||
26 | vgpu_gm20b_init_gr_ops(&g->ops); | ||
27 | |||
28 | return 0; | ||
29 | } | ||
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c index 99754cae..60a8f6c5 100644 --- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c | |||
@@ -601,36 +601,18 @@ static int vgpu_gr_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr, | |||
601 | return 0; | 601 | return 0; |
602 | } | 602 | } |
603 | 603 | ||
604 | static void vgpu_gr_detect_sm_arch(struct gk20a *g) | 604 | static u32 vgpu_gr_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) |
605 | { | 605 | { |
606 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); | 606 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); |
607 | u32 v = 0, raw_version, version = 0; | 607 | u32 data; |
608 | 608 | ||
609 | gk20a_dbg_fn(""); | 609 | WARN_ON(gpc_index > 0); |
610 | 610 | ||
611 | if (vgpu_get_attribute(platform->virt_handle, | 611 | if (vgpu_get_attribute(platform->virt_handle, |
612 | TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH, &v)) | 612 | TEGRA_VGPU_ATTRIB_GPC0_TPC_MASK, &data)) |
613 | gk20a_err(dev_from_gk20a(g), "failed to retrieve SM arch"); | 613 | gk20a_err(dev_from_gk20a(g), "failed to retrieve gpc0_tpc_mask"); |
614 | |||
615 | raw_version = gr_gpc0_tpc0_sm_arch_spa_version_v(v); | ||
616 | if (raw_version == gr_gpc0_tpc0_sm_arch_spa_version_smkepler_lp_v()) | ||
617 | version = 0x320; /* SM 3.2 */ | ||
618 | else | ||
619 | gk20a_err(dev_from_gk20a(g), "Unknown SM version 0x%x", | ||
620 | raw_version); | ||
621 | |||
622 | /* on Kepler, SM version == SPA version */ | ||
623 | g->gpu_characteristics.sm_arch_spa_version = version; | ||
624 | g->gpu_characteristics.sm_arch_sm_version = version; | ||
625 | |||
626 | g->gpu_characteristics.sm_arch_warp_count = | ||
627 | gr_gpc0_tpc0_sm_arch_warp_count_v(v); | ||
628 | } | ||
629 | 614 | ||
630 | static u32 vgpu_gr_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | 615 | return data; |
631 | { | ||
632 | /* One TPC for gk20a */ | ||
633 | return 0x1; | ||
634 | } | 616 | } |
635 | 617 | ||
636 | static u32 vgpu_gr_get_max_fbps_count(struct gk20a *g) | 618 | static u32 vgpu_gr_get_max_fbps_count(struct gk20a *g) |
@@ -661,6 +643,40 @@ static u32 vgpu_gr_get_fbp_en_mask(struct gk20a *g) | |||
661 | return fbp_en_mask; | 643 | return fbp_en_mask; |
662 | } | 644 | } |
663 | 645 | ||
646 | static u32 vgpu_gr_get_max_ltc_per_fbp(struct gk20a *g) | ||
647 | { | ||
648 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); | ||
649 | u32 val = 0; | ||
650 | |||
651 | gk20a_dbg_fn(""); | ||
652 | |||
653 | if (vgpu_get_attribute(platform->virt_handle, | ||
654 | TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP, &val)) | ||
655 | gk20a_err(dev_from_gk20a(g), "failed to retrieve max ltc per fbp"); | ||
656 | |||
657 | return val; | ||
658 | } | ||
659 | |||
660 | static u32 vgpu_gr_get_max_lts_per_ltc(struct gk20a *g) | ||
661 | { | ||
662 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); | ||
663 | u32 val = 0; | ||
664 | |||
665 | gk20a_dbg_fn(""); | ||
666 | |||
667 | if (vgpu_get_attribute(platform->virt_handle, | ||
668 | TEGRA_VGPU_ATTRIB_MAX_LTS_PER_LTC, &val)) | ||
669 | gk20a_err(dev_from_gk20a(g), "failed to retrieve lts per ltc"); | ||
670 | |||
671 | return val; | ||
672 | } | ||
673 | |||
674 | static u32 *vgpu_gr_rop_l2_en_mask(struct gk20a *g) | ||
675 | { | ||
676 | /* no one use it yet */ | ||
677 | return NULL; | ||
678 | } | ||
679 | |||
664 | static int vgpu_gr_add_zbc(struct gk20a *g, struct gr_gk20a *gr, | 680 | static int vgpu_gr_add_zbc(struct gk20a *g, struct gr_gk20a *gr, |
665 | struct zbc_entry *zbc_val) | 681 | struct zbc_entry *zbc_val) |
666 | { | 682 | { |
@@ -875,10 +891,12 @@ void vgpu_init_gr_ops(struct gpu_ops *gops) | |||
875 | gops->gr.free_obj_ctx = vgpu_gr_free_obj_ctx; | 891 | gops->gr.free_obj_ctx = vgpu_gr_free_obj_ctx; |
876 | gops->gr.bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull; | 892 | gops->gr.bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull; |
877 | gops->gr.get_zcull_info = vgpu_gr_get_zcull_info; | 893 | gops->gr.get_zcull_info = vgpu_gr_get_zcull_info; |
878 | gops->gr.detect_sm_arch = vgpu_gr_detect_sm_arch; | ||
879 | gops->gr.get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask; | 894 | gops->gr.get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask; |
880 | gops->gr.get_max_fbps_count = vgpu_gr_get_max_fbps_count; | 895 | gops->gr.get_max_fbps_count = vgpu_gr_get_max_fbps_count; |
881 | gops->gr.get_fbp_en_mask = vgpu_gr_get_fbp_en_mask; | 896 | gops->gr.get_fbp_en_mask = vgpu_gr_get_fbp_en_mask; |
897 | gops->gr.get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp; | ||
898 | gops->gr.get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc; | ||
899 | gops->gr.get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask; | ||
882 | gops->gr.zbc_set_table = vgpu_gr_add_zbc; | 900 | gops->gr.zbc_set_table = vgpu_gr_add_zbc; |
883 | gops->gr.zbc_query_table = vgpu_gr_query_zbc; | 901 | gops->gr.zbc_query_table = vgpu_gr_query_zbc; |
884 | } | 902 | } |
diff --git a/drivers/gpu/nvgpu/vgpu/ltc_vgpu.c b/drivers/gpu/nvgpu/vgpu/ltc_vgpu.c index 211e34b5..199e880b 100644 --- a/drivers/gpu/nvgpu/vgpu/ltc_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/ltc_vgpu.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Virtualized GPU L2 | 2 | * Virtualized GPU L2 |
3 | * | 3 | * |
4 | * Copyright (c) 2014 NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2015 NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -24,7 +24,7 @@ static int vgpu_determine_L2_size_bytes(struct gk20a *g) | |||
24 | 24 | ||
25 | if (vgpu_get_attribute(platform->virt_handle, | 25 | if (vgpu_get_attribute(platform->virt_handle, |
26 | TEGRA_VGPU_ATTRIB_L2_SIZE, &cache_size)) | 26 | TEGRA_VGPU_ATTRIB_L2_SIZE, &cache_size)) |
27 | dev_err(dev_from_gk20a(g), "unable to get L2 size"); | 27 | dev_err(dev_from_gk20a(g), "unable to get L2 size\n"); |
28 | 28 | ||
29 | return cache_size; | 29 | return cache_size; |
30 | } | 30 | } |
@@ -33,11 +33,26 @@ static int vgpu_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | |||
33 | { | 33 | { |
34 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); | 34 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); |
35 | u32 max_comptag_lines = 0; | 35 | u32 max_comptag_lines = 0; |
36 | int err; | ||
36 | 37 | ||
37 | gk20a_dbg_fn(""); | 38 | gk20a_dbg_fn(""); |
38 | 39 | ||
39 | vgpu_get_attribute(platform->virt_handle, | 40 | err = vgpu_get_attribute(platform->virt_handle, |
41 | TEGRA_VGPU_ATTRIB_CACHELINE_SIZE, | ||
42 | &gr->cacheline_size); | ||
43 | err |= vgpu_get_attribute(platform->virt_handle, | ||
44 | TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE, | ||
45 | &gr->comptags_per_cacheline); | ||
46 | err |= vgpu_get_attribute(platform->virt_handle, | ||
47 | TEGRA_VGPU_ATTRIB_SLICES_PER_LTC, | ||
48 | &gr->slices_per_ltc); | ||
49 | err |= vgpu_get_attribute(platform->virt_handle, | ||
40 | TEGRA_VGPU_ATTRIB_COMPTAG_LINES, &max_comptag_lines); | 50 | TEGRA_VGPU_ATTRIB_COMPTAG_LINES, &max_comptag_lines); |
51 | if (err) { | ||
52 | dev_err(dev_from_gk20a(g), "failed to get ctags atributes\n"); | ||
53 | return -ENXIO; | ||
54 | } | ||
55 | |||
41 | if (max_comptag_lines < 2) | 56 | if (max_comptag_lines < 2) |
42 | return -ENXIO; | 57 | return -ENXIO; |
43 | 58 | ||
@@ -46,8 +61,23 @@ static int vgpu_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | |||
46 | return 0; | 61 | return 0; |
47 | } | 62 | } |
48 | 63 | ||
64 | static void vgpu_ltc_init_fs_state(struct gk20a *g) | ||
65 | { | ||
66 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); | ||
67 | u32 ltc_count = 0; | ||
68 | int err; | ||
69 | |||
70 | gk20a_dbg_fn(""); | ||
71 | |||
72 | err = vgpu_get_attribute(platform->virt_handle, | ||
73 | TEGRA_VGPU_ATTRIB_LTC_COUNT, <c_count); | ||
74 | WARN_ON(err); | ||
75 | g->ltc_count = ltc_count; | ||
76 | } | ||
77 | |||
49 | void vgpu_init_ltc_ops(struct gpu_ops *gops) | 78 | void vgpu_init_ltc_ops(struct gpu_ops *gops) |
50 | { | 79 | { |
51 | gops->ltc.determine_L2_size_bytes = vgpu_determine_L2_size_bytes; | 80 | gops->ltc.determine_L2_size_bytes = vgpu_determine_L2_size_bytes; |
52 | gops->ltc.init_comptags = vgpu_ltc_init_comptags; | 81 | gops->ltc.init_comptags = vgpu_ltc_init_comptags; |
82 | gops->ltc.init_fs_state = vgpu_ltc_init_fs_state; | ||
53 | } | 83 | } |
diff --git a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c index 640111b5..c73037b6 100644 --- a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c | |||
@@ -282,6 +282,7 @@ static int vgpu_vm_alloc_share(struct gk20a_as_share *as_share, | |||
282 | msg.cmd = TEGRA_VGPU_CMD_AS_ALLOC_SHARE; | 282 | msg.cmd = TEGRA_VGPU_CMD_AS_ALLOC_SHARE; |
283 | msg.handle = platform->virt_handle; | 283 | msg.handle = platform->virt_handle; |
284 | p->size = vm->va_limit; | 284 | p->size = vm->va_limit; |
285 | p->big_page_size = vm->big_page_size; | ||
285 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | 286 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); |
286 | if (err || msg.ret) { | 287 | if (err || msg.ret) { |
287 | err = -ENOMEM; | 288 | err = -ENOMEM; |
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.c b/drivers/gpu/nvgpu/vgpu/vgpu.c index b16fe47c..b2c08d68 100644 --- a/drivers/gpu/nvgpu/vgpu/vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/vgpu.c | |||
@@ -22,6 +22,8 @@ | |||
22 | #include "gk20a/hal_gk20a.h" | 22 | #include "gk20a/hal_gk20a.h" |
23 | #include "gk20a/hw_mc_gk20a.h" | 23 | #include "gk20a/hw_mc_gk20a.h" |
24 | 24 | ||
25 | #include "gm20b/hal_gm20b.h" | ||
26 | |||
25 | static inline int vgpu_comm_init(struct platform_device *pdev) | 27 | static inline int vgpu_comm_init(struct platform_device *pdev) |
26 | { | 28 | { |
27 | size_t queue_sizes[] = { TEGRA_VGPU_QUEUE_SIZES }; | 29 | size_t queue_sizes[] = { TEGRA_VGPU_QUEUE_SIZES }; |
@@ -243,27 +245,38 @@ static void vgpu_detect_chip(struct gk20a *g) | |||
243 | g->gpu_characteristics.rev); | 245 | g->gpu_characteristics.rev); |
244 | } | 246 | } |
245 | 247 | ||
248 | void vgpu_init_hal_common(struct gk20a *g) | ||
249 | { | ||
250 | struct gpu_ops *gops = &g->ops; | ||
251 | |||
252 | vgpu_init_fifo_ops(gops); | ||
253 | vgpu_init_gr_ops(gops); | ||
254 | vgpu_init_ltc_ops(gops); | ||
255 | vgpu_init_mm_ops(gops); | ||
256 | vgpu_init_debug_ops(gops); | ||
257 | } | ||
258 | |||
246 | static int vgpu_init_hal(struct gk20a *g) | 259 | static int vgpu_init_hal(struct gk20a *g) |
247 | { | 260 | { |
248 | u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; | 261 | u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; |
262 | int err; | ||
249 | 263 | ||
250 | switch (ver) { | 264 | switch (ver) { |
251 | case GK20A_GPUID_GK20A: | 265 | case GK20A_GPUID_GK20A: |
252 | gk20a_dbg_info("gk20a detected"); | 266 | gk20a_dbg_info("gk20a detected"); |
253 | /* init gk20a ops then override with virt extensions */ | 267 | err = vgpu_gk20a_init_hal(g); |
254 | gk20a_init_hal(g); | 268 | break; |
255 | vgpu_init_fifo_ops(&g->ops); | 269 | case GK20A_GPUID_GM20B: |
256 | vgpu_init_gr_ops(&g->ops); | 270 | gk20a_dbg_info("gm20b detected"); |
257 | vgpu_init_ltc_ops(&g->ops); | 271 | err = vgpu_gm20b_init_hal(g); |
258 | vgpu_init_mm_ops(&g->ops); | ||
259 | vgpu_init_debug_ops(&g->ops); | ||
260 | break; | 272 | break; |
261 | default: | 273 | default: |
262 | gk20a_err(&g->dev->dev, "no support for %x", ver); | 274 | gk20a_err(&g->dev->dev, "no support for %x", ver); |
263 | return -ENODEV; | 275 | err = -ENODEV; |
276 | break; | ||
264 | } | 277 | } |
265 | 278 | ||
266 | return 0; | 279 | return err; |
267 | } | 280 | } |
268 | 281 | ||
269 | int vgpu_pm_finalize_poweron(struct device *dev) | 282 | int vgpu_pm_finalize_poweron(struct device *dev) |
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.h b/drivers/gpu/nvgpu/vgpu/vgpu.h index d577f32e..f1590593 100644 --- a/drivers/gpu/nvgpu/vgpu/vgpu.h +++ b/drivers/gpu/nvgpu/vgpu/vgpu.h | |||
@@ -46,6 +46,10 @@ int vgpu_init_fifo_support(struct gk20a *g); | |||
46 | int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value); | 46 | int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value); |
47 | int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in, | 47 | int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in, |
48 | size_t size_out); | 48 | size_t size_out); |
49 | |||
50 | void vgpu_init_hal_common(struct gk20a *g); | ||
51 | int vgpu_gk20a_init_hal(struct gk20a *g); | ||
52 | int vgpu_gm20b_init_hal(struct gk20a *g); | ||
49 | #else | 53 | #else |
50 | static inline int vgpu_pm_prepare_poweroff(struct device *dev) | 54 | static inline int vgpu_pm_prepare_poweroff(struct device *dev) |
51 | { | 55 | { |