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| author | Sandarbh Jain <sanjain@nvidia.com> | 2015-03-13 15:41:51 -0400 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-04-04 22:01:25 -0400 |
| commit | 95548fa880f3a31d900cfb9c4b2e30e7dfacadac (patch) | |
| tree | 4b35b21ce56e9953fe05b0ca6374240c743fccc9 /drivers/gpu/nvgpu/vgpu | |
| parent | 42e6b2f4512ce4481f2e5fd82e375e256173528e (diff) | |
gpu: nvgpu: GM20B extended buffer definition
Update extended buffer definition for Maxwell. On GM20B only PERF_CONTROL0 and
PERF_CONTROL5 registers are restored in extended buffer. They are needed for
stopping the counters as late as possible during ctx save and start them as
early as possible during context restore. On Maxwell, these registers contain
the enable/disable bit.
Bug 200086767
Change-Id: I59125a2f04bd0975be8a1ccecf993c9370f20337
Signed-off-by: Sandarbh Jain <sanjain@nvidia.com>
Reviewed-on: http://git-master/r/717421
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu')
0 files changed, 0 insertions, 0 deletions