diff options
author | Aingara Paramakuru <aparamakuru@nvidia.com> | 2015-09-29 12:57:37 -0400 |
---|---|---|
committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 04:52:09 -0500 |
commit | 9320d4711f3e39d90d27daae97211d8fc753ba37 (patch) | |
tree | 6e1ba0c5596f2e28f0ae6b1a22067656c1524757 /drivers/gpu/nvgpu/vgpu | |
parent | 428b9eb5523d478499c7ef023ea7287bf7ac617f (diff) |
gpu: nvgpu: vgpu: add interface to alloc ctxsw buffers
gp10b introduces support for preemption (GfxP and CILP).
Add a new interface to allow allocating buffers needed
to support this functionality.
Bug 1677153
Change-Id: I8578a7b0a4327f3496d852eeb8be5fc778e2c225
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/806963
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/817039
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c | 169 |
1 files changed, 169 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c index 9df29eee..5edaa819 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c | |||
@@ -11,10 +11,179 @@ | |||
11 | * more details. | 11 | * more details. |
12 | */ | 12 | */ |
13 | 13 | ||
14 | #include "vgpu/vgpu.h" | ||
14 | #include "vgpu_gr_gp10b.h" | 15 | #include "vgpu_gr_gp10b.h" |
15 | #include "vgpu/gm20b/vgpu_gr_gm20b.h" | 16 | #include "vgpu/gm20b/vgpu_gr_gm20b.h" |
16 | 17 | ||
18 | #include "gp10b/hw_gr_gp10b.h" | ||
19 | |||
20 | static void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, | ||
21 | struct gr_ctx_desc *gr_ctx) | ||
22 | { | ||
23 | gk20a_dbg_fn(""); | ||
24 | |||
25 | if (!gr_ctx || !gr_ctx->mem.gpu_va) | ||
26 | return; | ||
27 | |||
28 | gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.pagepool_ctxsw_buffer); | ||
29 | gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer); | ||
30 | gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer); | ||
31 | gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer); | ||
32 | vgpu_gr_free_gr_ctx(g, vm, gr_ctx); | ||
33 | } | ||
34 | |||
35 | static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, | ||
36 | struct gr_ctx_desc **__gr_ctx, | ||
37 | struct vm_gk20a *vm, | ||
38 | u32 class, | ||
39 | u32 flags) | ||
40 | { | ||
41 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); | ||
42 | struct tegra_vgpu_cmd_msg msg; | ||
43 | struct tegra_vgpu_gr_bind_ctxsw_buffers_params *p = | ||
44 | &msg.params.gr_bind_ctxsw_buffers; | ||
45 | struct gr_ctx_desc *gr_ctx = *__gr_ctx; | ||
46 | int err; | ||
47 | |||
48 | gk20a_dbg_fn(""); | ||
49 | |||
50 | WARN_ON(TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAX != | ||
51 | TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_LAST); | ||
52 | |||
53 | err = vgpu_gr_alloc_gr_ctx(g, __gr_ctx, vm, class, flags); | ||
54 | if (err) | ||
55 | return err; | ||
56 | |||
57 | if (class == PASCAL_A && g->gr.t18x.ctx_vars.force_preemption_gfxp) | ||
58 | flags |= NVGPU_ALLOC_OBJ_FLAGS_GFXP; | ||
59 | |||
60 | if (class == PASCAL_COMPUTE_A && | ||
61 | g->gr.t18x.ctx_vars.force_preemption_cilp) | ||
62 | flags |= NVGPU_ALLOC_OBJ_FLAGS_CILP; | ||
63 | |||
64 | if (flags & NVGPU_ALLOC_OBJ_FLAGS_GFXP) { | ||
65 | u32 spill_size = | ||
66 | gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() * | ||
67 | gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(); | ||
68 | u32 pagepool_size = g->ops.gr.pagepool_default_size(g) * | ||
69 | gr_scc_pagepool_total_pages_byte_granularity_v(); | ||
70 | u32 betacb_size = g->gr.attrib_cb_default_size + | ||
71 | (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - | ||
72 | gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); | ||
73 | u32 attrib_cb_size = (betacb_size + g->gr.alpha_cb_size) * | ||
74 | gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() * | ||
75 | g->gr.max_tpc_count; | ||
76 | struct mem_desc *desc; | ||
77 | |||
78 | attrib_cb_size = ALIGN(attrib_cb_size, 128); | ||
79 | |||
80 | gk20a_dbg_info("gfxp context preempt size=%d", | ||
81 | g->gr.t18x.ctx_vars.preempt_image_size); | ||
82 | gk20a_dbg_info("gfxp context spill size=%d", spill_size); | ||
83 | gk20a_dbg_info("gfxp context pagepool size=%d", pagepool_size); | ||
84 | gk20a_dbg_info("gfxp context attrib cb size=%d", | ||
85 | attrib_cb_size); | ||
86 | |||
87 | err = gk20a_gmmu_alloc_map(vm, | ||
88 | g->gr.t18x.ctx_vars.preempt_image_size, | ||
89 | &gr_ctx->t18x.preempt_ctxsw_buffer); | ||
90 | if (err) { | ||
91 | err = -ENOMEM; | ||
92 | goto fail; | ||
93 | } | ||
94 | desc = &gr_ctx->t18x.preempt_ctxsw_buffer; | ||
95 | p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->gpu_va; | ||
96 | p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->size; | ||
97 | |||
98 | err = gk20a_gmmu_alloc_map(vm, spill_size, | ||
99 | &gr_ctx->t18x.spill_ctxsw_buffer); | ||
100 | if (err) { | ||
101 | err = -ENOMEM; | ||
102 | goto fail; | ||
103 | } | ||
104 | desc = &gr_ctx->t18x.spill_ctxsw_buffer; | ||
105 | p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->gpu_va; | ||
106 | p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->size; | ||
107 | |||
108 | err = gk20a_gmmu_alloc_map(vm, pagepool_size, | ||
109 | &gr_ctx->t18x.pagepool_ctxsw_buffer); | ||
110 | if (err) { | ||
111 | err = -ENOMEM; | ||
112 | goto fail; | ||
113 | } | ||
114 | desc = &gr_ctx->t18x.pagepool_ctxsw_buffer; | ||
115 | p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = | ||
116 | desc->gpu_va; | ||
117 | p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = desc->size; | ||
118 | |||
119 | err = gk20a_gmmu_alloc_map(vm, attrib_cb_size, | ||
120 | &gr_ctx->t18x.betacb_ctxsw_buffer); | ||
121 | if (err) { | ||
122 | err = -ENOMEM; | ||
123 | goto fail; | ||
124 | } | ||
125 | desc = &gr_ctx->t18x.betacb_ctxsw_buffer; | ||
126 | p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = | ||
127 | desc->gpu_va; | ||
128 | p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = desc->size; | ||
129 | |||
130 | gr_ctx->preempt_mode = NVGPU_GR_PREEMPTION_MODE_GFXP; | ||
131 | p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_GFX_GFXP; | ||
132 | } | ||
133 | |||
134 | if (class == PASCAL_COMPUTE_A) { | ||
135 | if (flags & NVGPU_ALLOC_OBJ_FLAGS_CILP) { | ||
136 | gr_ctx->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CILP; | ||
137 | p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CILP; | ||
138 | } else { | ||
139 | gr_ctx->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CTA; | ||
140 | p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CTA; | ||
141 | } | ||
142 | } | ||
143 | |||
144 | if (gr_ctx->preempt_mode) { | ||
145 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS; | ||
146 | msg.handle = platform->virt_handle; | ||
147 | p->handle = gr_ctx->virt_ctx; | ||
148 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
149 | if (err || msg.ret) { | ||
150 | err = -ENOMEM; | ||
151 | goto fail; | ||
152 | } | ||
153 | } | ||
154 | |||
155 | gk20a_dbg_fn("done"); | ||
156 | return err; | ||
157 | |||
158 | fail: | ||
159 | vgpu_gr_gp10b_free_gr_ctx(g, vm, gr_ctx); | ||
160 | return err; | ||
161 | } | ||
162 | |||
163 | static int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g) | ||
164 | { | ||
165 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); | ||
166 | int err; | ||
167 | |||
168 | gk20a_dbg_fn(""); | ||
169 | |||
170 | err = vgpu_gr_init_ctx_state(g); | ||
171 | if (err) | ||
172 | return err; | ||
173 | |||
174 | vgpu_get_attribute(platform->virt_handle, | ||
175 | TEGRA_VGPU_ATTRIB_PREEMPT_CTX_SIZE, | ||
176 | &g->gr.t18x.ctx_vars.preempt_image_size); | ||
177 | if (!g->gr.t18x.ctx_vars.preempt_image_size) | ||
178 | return -ENXIO; | ||
179 | |||
180 | return 0; | ||
181 | } | ||
182 | |||
17 | void vgpu_gp10b_init_gr_ops(struct gpu_ops *gops) | 183 | void vgpu_gp10b_init_gr_ops(struct gpu_ops *gops) |
18 | { | 184 | { |
19 | vgpu_gm20b_init_gr_ops(gops); | 185 | vgpu_gm20b_init_gr_ops(gops); |
186 | gops->gr.alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx; | ||
187 | gops->gr.free_gr_ctx = vgpu_gr_gp10b_free_gr_ctx; | ||
188 | gops->gr.init_ctx_state = vgpu_gr_gp10b_init_ctx_state; | ||
20 | } | 189 | } |