diff options
author | Aingara Paramakuru <aparamakuru@nvidia.com> | 2015-04-15 16:10:30 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2015-06-22 11:56:36 -0400 |
commit | 788776c9aa2028a0672c07271e9c06ed684f74a8 (patch) | |
tree | 7afe8a93d8076ffc3cf77279f4954f096c795492 /drivers/gpu/nvgpu/vgpu | |
parent | f877d0649c40c183f02953b192b0a352e5153851 (diff) |
gpu: nvgpu: vgpu: support additional notifications
Client notification support is now added for the following:
- stalling and non-stalling GR sema release
- non-stalling FIFO channel intr
- non-stalling CE2 nonblockpipe intr
Bug 200097077
Change-Id: Icd3c076d7880e1c9ef1fcc0fc58eed9f23f39277
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/736064
(cherry picked from commit 0585d1f14d5a5ae1ccde8ccb7b7daa5593b3d1bc)
Reviewed-on: http://git-master/r/759824
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/ce2_vgpu.c | 33 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 17 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gr_vgpu.c | 24 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/vgpu.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/vgpu.h | 6 |
5 files changed, 86 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/ce2_vgpu.c b/drivers/gpu/nvgpu/vgpu/ce2_vgpu.c new file mode 100644 index 00000000..631461f9 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/ce2_vgpu.c | |||
@@ -0,0 +1,33 @@ | |||
1 | /* | ||
2 | * Virtualized GPU CE2 | ||
3 | * | ||
4 | * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #include "vgpu/vgpu.h" | ||
17 | |||
18 | int vgpu_ce2_nonstall_isr(struct gk20a *g, | ||
19 | struct tegra_vgpu_ce2_nonstall_intr_info *info) | ||
20 | { | ||
21 | gk20a_dbg_fn(""); | ||
22 | |||
23 | switch (info->type) { | ||
24 | case TEGRA_VGPU_CE2_NONSTALL_INTR_NONBLOCKPIPE: | ||
25 | gk20a_channel_semaphore_wakeup(g); | ||
26 | break; | ||
27 | default: | ||
28 | WARN_ON(1); | ||
29 | break; | ||
30 | } | ||
31 | |||
32 | return 0; | ||
33 | } | ||
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index 23ff8677..84bb3646 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | |||
@@ -566,6 +566,23 @@ int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info) | |||
566 | return 0; | 566 | return 0; |
567 | } | 567 | } |
568 | 568 | ||
569 | int vgpu_fifo_nonstall_isr(struct gk20a *g, | ||
570 | struct tegra_vgpu_fifo_nonstall_intr_info *info) | ||
571 | { | ||
572 | gk20a_dbg_fn(""); | ||
573 | |||
574 | switch (info->type) { | ||
575 | case TEGRA_VGPU_FIFO_NONSTALL_INTR_CHANNEL: | ||
576 | gk20a_channel_semaphore_wakeup(g); | ||
577 | break; | ||
578 | default: | ||
579 | WARN_ON(1); | ||
580 | break; | ||
581 | } | ||
582 | |||
583 | return 0; | ||
584 | } | ||
585 | |||
569 | void vgpu_init_fifo_ops(struct gpu_ops *gops) | 586 | void vgpu_init_fifo_ops(struct gpu_ops *gops) |
570 | { | 587 | { |
571 | gops->fifo.bind_channel = vgpu_channel_bind; | 588 | gops->fifo.bind_channel = vgpu_channel_bind; |
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c index f6f12c7b..99754cae 100644 --- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c | |||
@@ -803,7 +803,8 @@ int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info) | |||
803 | struct channel_gk20a *ch = &f->channel[info->chid]; | 803 | struct channel_gk20a *ch = &f->channel[info->chid]; |
804 | 804 | ||
805 | gk20a_dbg_fn(""); | 805 | gk20a_dbg_fn(""); |
806 | if (info->type != TEGRA_VGPU_GR_INTR_NOTIFY) | 806 | if (info->type != TEGRA_VGPU_GR_INTR_NOTIFY && |
807 | info->type != TEGRA_VGPU_GR_INTR_SEMAPHORE) | ||
807 | gk20a_err(dev_from_gk20a(g), "gr intr (%d) on ch %u", | 808 | gk20a_err(dev_from_gk20a(g), "gr intr (%d) on ch %u", |
808 | info->type, info->chid); | 809 | info->type, info->chid); |
809 | 810 | ||
@@ -811,6 +812,10 @@ int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info) | |||
811 | case TEGRA_VGPU_GR_INTR_NOTIFY: | 812 | case TEGRA_VGPU_GR_INTR_NOTIFY: |
812 | wake_up(&ch->notifier_wq); | 813 | wake_up(&ch->notifier_wq); |
813 | break; | 814 | break; |
815 | case TEGRA_VGPU_GR_INTR_SEMAPHORE: | ||
816 | gk20a_channel_event(ch); | ||
817 | wake_up(&ch->semaphore_wq); | ||
818 | break; | ||
814 | case TEGRA_VGPU_GR_INTR_SEMAPHORE_TIMEOUT: | 819 | case TEGRA_VGPU_GR_INTR_SEMAPHORE_TIMEOUT: |
815 | gk20a_set_error_notifier(ch, | 820 | gk20a_set_error_notifier(ch, |
816 | NVGPU_CHANNEL_GR_SEMAPHORE_TIMEOUT); | 821 | NVGPU_CHANNEL_GR_SEMAPHORE_TIMEOUT); |
@@ -846,6 +851,23 @@ int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info) | |||
846 | return 0; | 851 | return 0; |
847 | } | 852 | } |
848 | 853 | ||
854 | int vgpu_gr_nonstall_isr(struct gk20a *g, | ||
855 | struct tegra_vgpu_gr_nonstall_intr_info *info) | ||
856 | { | ||
857 | gk20a_dbg_fn(""); | ||
858 | |||
859 | switch (info->type) { | ||
860 | case TEGRA_VGPU_GR_NONSTALL_INTR_SEMAPHORE: | ||
861 | gk20a_channel_semaphore_wakeup(g); | ||
862 | break; | ||
863 | default: | ||
864 | WARN_ON(1); | ||
865 | break; | ||
866 | } | ||
867 | |||
868 | return 0; | ||
869 | } | ||
870 | |||
849 | void vgpu_init_gr_ops(struct gpu_ops *gops) | 871 | void vgpu_init_gr_ops(struct gpu_ops *gops) |
850 | { | 872 | { |
851 | gops->gr.free_channel_ctx = vgpu_gr_free_channel_ctx; | 873 | gops->gr.free_channel_ctx = vgpu_gr_free_channel_ctx; |
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.c b/drivers/gpu/nvgpu/vgpu/vgpu.c index c998b10b..b16fe47c 100644 --- a/drivers/gpu/nvgpu/vgpu/vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/vgpu.c | |||
@@ -114,8 +114,15 @@ static int vgpu_intr_thread(void *dev_id) | |||
114 | 114 | ||
115 | if (msg->unit == TEGRA_VGPU_INTR_GR) | 115 | if (msg->unit == TEGRA_VGPU_INTR_GR) |
116 | vgpu_gr_isr(g, &msg->info.gr_intr); | 116 | vgpu_gr_isr(g, &msg->info.gr_intr); |
117 | else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_GR) | ||
118 | vgpu_gr_nonstall_isr(g, &msg->info.gr_nonstall_intr); | ||
117 | else if (msg->unit == TEGRA_VGPU_INTR_FIFO) | 119 | else if (msg->unit == TEGRA_VGPU_INTR_FIFO) |
118 | vgpu_fifo_isr(g, &msg->info.fifo_intr); | 120 | vgpu_fifo_isr(g, &msg->info.fifo_intr); |
121 | else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_FIFO) | ||
122 | vgpu_fifo_nonstall_isr(g, | ||
123 | &msg->info.fifo_nonstall_intr); | ||
124 | else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_CE2) | ||
125 | vgpu_ce2_nonstall_isr(g, &msg->info.ce2_nonstall_intr); | ||
119 | 126 | ||
120 | tegra_gr_comm_release(handle); | 127 | tegra_gr_comm_release(handle); |
121 | } | 128 | } |
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.h b/drivers/gpu/nvgpu/vgpu/vgpu.h index 1a7ef7ba..d577f32e 100644 --- a/drivers/gpu/nvgpu/vgpu/vgpu.h +++ b/drivers/gpu/nvgpu/vgpu/vgpu.h | |||
@@ -27,7 +27,13 @@ int vgpu_probe(struct platform_device *dev); | |||
27 | int vgpu_remove(struct platform_device *dev); | 27 | int vgpu_remove(struct platform_device *dev); |
28 | u64 vgpu_bar1_map(struct gk20a *g, struct sg_table **sgt, u64 size); | 28 | u64 vgpu_bar1_map(struct gk20a *g, struct sg_table **sgt, u64 size); |
29 | int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info); | 29 | int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info); |
30 | int vgpu_gr_nonstall_isr(struct gk20a *g, | ||
31 | struct tegra_vgpu_gr_nonstall_intr_info *info); | ||
30 | int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info); | 32 | int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info); |
33 | int vgpu_fifo_nonstall_isr(struct gk20a *g, | ||
34 | struct tegra_vgpu_fifo_nonstall_intr_info *info); | ||
35 | int vgpu_ce2_nonstall_isr(struct gk20a *g, | ||
36 | struct tegra_vgpu_ce2_nonstall_intr_info *info); | ||
31 | void vgpu_init_fifo_ops(struct gpu_ops *gops); | 37 | void vgpu_init_fifo_ops(struct gpu_ops *gops); |
32 | void vgpu_init_gr_ops(struct gpu_ops *gops); | 38 | void vgpu_init_gr_ops(struct gpu_ops *gops); |
33 | void vgpu_init_ltc_ops(struct gpu_ops *gops); | 39 | void vgpu_init_ltc_ops(struct gpu_ops *gops); |