gpu: nvgpu: hal for timestamps correlation

In order to perform timestamps correlation for FECS
traces, we need to collect GPU / GPU timestamps
samples. In virtualization case, it is possible for
a guest to get GPU timestamps by using read_ptimer.
However, if the CPU timestamp is read on guest side,
and the GPU timestamp is read on vm-server side,
then it introduces some latency that will create an
artificial offset for GPU timestamps (~2 us in
average). For better CPU / GPU timestamps correlation,
Added a command to collect all timestamps on vm-server
side.

Bug 1900475

Change-Id: Idfdc6ae4c16c501dc5e00053a5b75932c55148d6
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1472447
(cherry picked from commit 56f56b5cd9d2e75cf7d2613b5e115bfebdbee0ce)
Reviewed-on: http://git-master/r/1489183
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 43 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.c b/drivers/gpu/nvgpu/vgpu/vgpu.c
index cdd0d378..a8c28826 100644
--- a/drivers/gpu/nvgpu/vgpu/vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/vgpu.c
@@ -367,6 +367,48 @@ static int vgpu_read_ptimer(struct gk20a *g, u64 *value)
         return err;
 }
 
+int vgpu_get_timestamps_zipper(struct gk20a *g,
+                u32 source_id, u32 count,
+                struct nvgpu_cpu_time_correlation_sample *samples)
+{
+        struct tegra_vgpu_cmd_msg msg = {0};
+        struct tegra_vgpu_get_timestamps_zipper_params *p =
+                        &msg.params.get_timestamps_zipper;
+        int err;
+        u32 i;
+
+        gk20a_dbg_fn("");
+
+        if (count > TEGRA_VGPU_GET_TIMESTAMPS_ZIPPER_MAX_COUNT) {
+                nvgpu_err(g, "count %u overflow", count);
+                return -EINVAL;
+        }
+
+        if (source_id != NVGPU_GPU_GET_CPU_TIME_CORRELATION_INFO_SRC_ID_TSC) {
+                nvgpu_err(g, "source_id %u not supported", source_id);
+                return -EINVAL;
+        }
+
+        msg.cmd = TEGRA_VGPU_CMD_GET_TIMESTAMPS_ZIPPER;
+        msg.handle = vgpu_get_handle(g);
+        p->source_id = TEGRA_VGPU_GET_TIMESTAMPS_ZIPPER_SRC_ID_TSC;
+        p->count = count;
+
+        err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
+        err = err ? err : msg.ret;
+        if (err) {
+                nvgpu_err(g, "vgpu get timestamps zipper failed, err=%d", err);
+                return err;
+        }
+
+        for (i = 0; i < count; i++) {
+                samples[i].cpu_timestamp = p->samples[i].cpu_timestamp;
+                samples[i].gpu_timestamp = p->samples[i].gpu_timestamp;
+        }
+
+        return err;
+}
+
 void vgpu_init_hal_common(struct gk20a *g)
 {
         struct gpu_ops *gops = &g->ops;
@@ -384,6 +426,7 @@ void vgpu_init_hal_common(struct gk20a *g)
 #endif
         gops->chip_init_gpu_characteristics = vgpu_init_gpu_characteristics;
         gops->bus.read_ptimer = vgpu_read_ptimer;
+        gops->bus.get_timestamps_zipper = vgpu_get_timestamps_zipper;
 }
 
 static int vgpu_init_hal(struct gk20a *g)