gpu: nvgpu: deprecate TSG/CHANNEL_SET_PRIORITY IOCTLs

TSG/CHANNEL_SET_PRIORITY IOCTLs are deprecated and user space should be using
combination of timeslice and interleave levels to decide the priority

Hence remove the IOCTLs and all corresponding APIs

Jira NVGPU-393

Change-Id: I7cf0785689269536eca0c278c774b0e9e74f8c2f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1598581
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

4 files changed, 0 insertions, 22 deletions

diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
index fa9388f2..66b2dbef 100644
--- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
@@ -607,25 +607,6 @@ int vgpu_fifo_wait_engine_idle(struct gk20a *g)
         return 0;
 }
 
-int vgpu_channel_set_priority(struct channel_gk20a *ch, u32 priority)
-{
-        struct tegra_vgpu_cmd_msg msg;
-        struct tegra_vgpu_channel_priority_params *p =
-                        &msg.params.channel_priority;
-        int err;
-
-        gk20a_dbg_info("channel %d set priority %u", ch->chid, priority);
-
-        msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY;
-        msg.handle = vgpu_get_handle(ch->g);
-        p->handle = ch->virt_ctx;
-        p->priority = priority;
-        err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
-        WARN_ON(err || msg.ret);
-
-        return err ? err : msg.ret;
-}
-
 static int vgpu_fifo_tsg_set_runlist_interleave(struct gk20a *g,
                                         u32 tsgid,
                                         u32 runlist_id,
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h
index aa95cc41..7633ad95 100644
--- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h
+++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h
@@ -46,7 +46,6 @@ int vgpu_fifo_preempt_tsg(struct gk20a *g, u32 tsgid);
 int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id,
                                 u32 chid, bool add, bool wait_for_finish);
 int vgpu_fifo_wait_engine_idle(struct gk20a *g);
-int vgpu_channel_set_priority(struct channel_gk20a *ch, u32 priority);
 int vgpu_fifo_set_runlist_interleave(struct gk20a *g,
                                         u32 id,
                                         bool is_tsg,
diff --git a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c
index 37a34950..a3eb59ac 100644
--- a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c
+++ b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c
@@ -264,7 +264,6 @@ static const struct gpu_ops vgpu_gm20b_ops = {
                 .alloc_inst = vgpu_channel_alloc_inst,
                 .free_inst = vgpu_channel_free_inst,
                 .setup_ramfc = vgpu_channel_setup_ramfc,
-                .channel_set_priority = vgpu_channel_set_priority,
                 .channel_set_timeslice = vgpu_channel_set_timeslice,
                 .default_timeslice_us = vgpu_fifo_default_timeslice_us,
                 .setup_userd = gk20a_fifo_setup_userd,
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
index 693709ef..55448f3b 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -289,7 +289,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
                 .alloc_inst = vgpu_channel_alloc_inst,
                 .free_inst = vgpu_channel_free_inst,
                 .setup_ramfc = vgpu_channel_setup_ramfc,
-                .channel_set_priority = vgpu_channel_set_priority,
                 .channel_set_timeslice = vgpu_channel_set_timeslice,
                 .default_timeslice_us = vgpu_fifo_default_timeslice_us,
                 .setup_userd = gk20a_fifo_setup_userd,