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authorVaibhav Kachore <vkachore@nvidia.com>2018-09-11 05:47:07 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-26 02:04:16 -0400
commit2ab564937e5e4607e1734690101d07b66e5981d2 (patch)
tree03b51736c8d6754b62e7bf23cac83068e1b31956 /drivers/gpu/nvgpu/vgpu
parent3f83528d769169fdaf25912f425226eaa07427f0 (diff)
gpu: nvgpu: enable HWPM Mode-E context switch
- This patch enables HWPM Mode-E context switch for gv11b. - Write new pm mode to context buffer header. Ucode use this mode to enable mode-e context switch. This is Mode-B context switch of PMs with Mode-E streamout on one context. If this mode is set, Ucode makes sure that Mode-E pipe (perfmons, routers, pma) is idle before it context switches PMs. - This allows us to collect counters in a secure way (i.e. on context basis) with stream out. - For Mode-E ctxsw it is required that engine_sel is set to 0xFFFFFFFF. - Default 0 is a valid signal and causes problems. Bug 2106999 Change-Id: Idc6380116a71ffd7ae348ceec68cb395b2eca5f6 Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1818070 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu')
-rw-r--r--drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
index eac57433..1fc1b0f2 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -81,6 +81,8 @@
81#include <gv11b/gr_ctx_gv11b.h> 81#include <gv11b/gr_ctx_gv11b.h>
82#include <gv11b/gr_gv11b.h> 82#include <gv11b/gr_gv11b.h>
83 83
84#include <gv100/gr_gv100.h>
85
84#include <nvgpu/enabled.h> 86#include <nvgpu/enabled.h>
85#include <nvgpu/channel.h> 87#include <nvgpu/channel.h>
86 88
@@ -183,6 +185,8 @@ static const struct gpu_ops vgpu_gv11b_ops = {
183 .enable_exceptions = NULL, 185 .enable_exceptions = NULL,
184 .get_lrf_tex_ltc_dram_override = NULL, 186 .get_lrf_tex_ltc_dram_override = NULL,
185 .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode, 187 .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode,
188 .get_hw_accessor_stream_out_mode =
189 gr_gv100_get_hw_accessor_stream_out_mode,
186 .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode, 190 .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode,
187 .record_sm_error_state = gv11b_gr_record_sm_error_state, 191 .record_sm_error_state = gv11b_gr_record_sm_error_state,
188 .clear_sm_error_state = vgpu_gr_clear_sm_error_state, 192 .clear_sm_error_state = vgpu_gr_clear_sm_error_state,