diff options
author | Richard Zhao <rizhao@nvidia.com> | 2016-05-09 18:25:44 -0400 |
---|---|---|
committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 04:56:16 -0500 |
commit | 2029134634fe5292f56ba049fef30fc85a5bcef0 (patch) | |
tree | 7dbb8ea7efb5035601daa041904fe8dcf3d34e0f /drivers/gpu/nvgpu/vgpu | |
parent | a334f78461a1d5a840275a3c55d9b5b41eeca699 (diff) |
gpu: nvgpu: vgpu: manage gr_ctx as independent resource
gr_ctx will managed as independent resource in RM server
and vgpu can get a gr_ctx handle.
Bug 1702773
Change-Id: Ifceb44b7d9a1ba03fc2a4df847f4a78ac4c4a0d4
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1144934
(cherry picked from commit 0da3101d9b59fe1f9a47ce7b70b30cb8919f35ac)
Reviewed-on: http://git-master/r/1150707
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c index 08793e18..3194fff1 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -21,7 +21,7 @@ static void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, | |||
21 | struct gr_ctx_desc *gr_ctx) | 21 | struct gr_ctx_desc *gr_ctx) |
22 | { | 22 | { |
23 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); | 23 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); |
24 | struct tegra_vgpu_cmd_msg msg; | 24 | struct tegra_vgpu_cmd_msg msg = {0}; |
25 | struct tegra_vgpu_gr_ctx_params *p = &msg.params.gr_ctx; | 25 | struct tegra_vgpu_gr_ctx_params *p = &msg.params.gr_ctx; |
26 | int err; | 26 | int err; |
27 | 27 | ||
@@ -30,9 +30,9 @@ static void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, | |||
30 | if (!gr_ctx || !gr_ctx->mem.gpu_va) | 30 | if (!gr_ctx || !gr_ctx->mem.gpu_va) |
31 | return; | 31 | return; |
32 | 32 | ||
33 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_FREE_GR_CTX; | 33 | msg.cmd = TEGRA_VGPU_CMD_GR_CTX_FREE; |
34 | msg.handle = platform->virt_handle; | 34 | msg.handle = platform->virt_handle; |
35 | p->handle = gr_ctx->virt_ctx; | 35 | p->gr_ctx_handle = gr_ctx->virt_ctx; |
36 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | 36 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); |
37 | WARN_ON(err || msg.ret); | 37 | WARN_ON(err || msg.ret); |
38 | 38 | ||
@@ -53,10 +53,10 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, | |||
53 | u32 flags) | 53 | u32 flags) |
54 | { | 54 | { |
55 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); | 55 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); |
56 | struct tegra_vgpu_cmd_msg msg; | 56 | struct tegra_vgpu_cmd_msg msg = {0}; |
57 | struct tegra_vgpu_gr_bind_ctxsw_buffers_params *p = | 57 | struct tegra_vgpu_gr_bind_ctxsw_buffers_params *p = |
58 | &msg.params.gr_bind_ctxsw_buffers; | 58 | &msg.params.gr_bind_ctxsw_buffers; |
59 | struct gr_ctx_desc *gr_ctx = *__gr_ctx; | 59 | struct gr_ctx_desc *gr_ctx; |
60 | int err; | 60 | int err; |
61 | 61 | ||
62 | gk20a_dbg_fn(""); | 62 | gk20a_dbg_fn(""); |
@@ -68,6 +68,8 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, | |||
68 | if (err) | 68 | if (err) |
69 | return err; | 69 | return err; |
70 | 70 | ||
71 | gr_ctx = *__gr_ctx; | ||
72 | |||
71 | if (class == PASCAL_A && g->gr.t18x.ctx_vars.force_preemption_gfxp) | 73 | if (class == PASCAL_A && g->gr.t18x.ctx_vars.force_preemption_gfxp) |
72 | flags |= NVGPU_ALLOC_OBJ_FLAGS_GFXP; | 74 | flags |= NVGPU_ALLOC_OBJ_FLAGS_GFXP; |
73 | 75 | ||
@@ -161,7 +163,7 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, | |||
161 | if (gr_ctx->graphics_preempt_mode || gr_ctx->compute_preempt_mode) { | 163 | if (gr_ctx->graphics_preempt_mode || gr_ctx->compute_preempt_mode) { |
162 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS; | 164 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS; |
163 | msg.handle = platform->virt_handle; | 165 | msg.handle = platform->virt_handle; |
164 | p->handle = gr_ctx->virt_ctx; | 166 | p->gr_ctx_handle = gr_ctx->virt_ctx; |
165 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | 167 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); |
166 | if (err || msg.ret) { | 168 | if (err || msg.ret) { |
167 | err = -ENOMEM; | 169 | err = -ENOMEM; |