gpu: nvgpu: Remove mm.get_iova_addr

Remove the mm.get_iova_addr() HAL and replace it with a new HAL
called mm.gpu_phys_addr(). This new HAL provides the real phys
address that should be passed to the GPU from a physical address
obtained from a scatter list. It also provides a mechanism by
which the HAL code can add extra bits to a GPU physical address
based on the attributes passed in. This is necessary during GMMU
page table programming.

Also remove the flags argument from the various address functions.
This flag was used for adding an IO coherence bit to the GPU
physical address which is not supported.

JIRA NVGPU-30

Change-Id: I69af5b1c6bd905c4077c26c098fac101c6b41a33
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1530864
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 8 insertions, 5 deletions

diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
index 520771a7..f1ae2f1f 100644
--- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
@@ -308,8 +308,8 @@ static int vgpu_init_fifo_setup_sw(struct gk20a *g)
 
         for (chid = 0; chid < f->num_channels; chid++) {
                 f->channel[chid].userd_iova =
-                        g->ops.mm.get_iova_addr(g, f->userd.priv.sgt->sgl, 0)
-                                + chid * f->userd_entry_size;
+                        nvgpu_mem_get_addr(g, &f->userd) +
+                        chid * f->userd_entry_size;
                 f->channel[chid].userd_gpu_va =
                         f->userd.gpu_va + chid * f->userd_entry_size;
 
diff --git a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c
index a4ffc7e8..ef9e00c8 100644
--- a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c
@@ -23,8 +23,11 @@
 
 #include <nvgpu/vgpu/vm.h>
 
+#include <nvgpu/linux/nvgpu_mem.h>
+
 #include "vgpu/vgpu.h"
 #include "gk20a/mm_gk20a.h"
+#include "gm20b/mm_gm20b.h"
 
 #include "common/linux/vm_priv.h"
 
@@ -95,7 +98,7 @@ static u64 vgpu_locked_gmmu_map(struct vm_gk20a *vm,
         struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(d);
         struct tegra_vgpu_cmd_msg msg;
         struct tegra_vgpu_as_map_params *p = &msg.params.as_map;
-        u64 addr = g->ops.mm.get_iova_addr(g, sgt->sgl, flags);
+        u64 addr = nvgpu_mem_get_addr_sgl(g, sgt->sgl);
         u8 prot;
 
         gk20a_dbg_fn("");
@@ -243,7 +246,7 @@ u64 vgpu_bar1_map(struct gk20a *g, struct sg_table **sgt, u64 size)
 {
         struct dma_iommu_mapping *mapping =
                         to_dma_iommu_mapping(dev_from_gk20a(g));
-        u64 addr = g->ops.mm.get_iova_addr(g, (*sgt)->sgl, 0);
+        u64 addr = nvgpu_mem_get_addr_sgl(g, (*sgt)->sgl);
         struct tegra_vgpu_cmd_msg msg;
         struct tegra_vgpu_as_map_params *p = &msg.params.as_map;
         int err;
@@ -368,6 +371,6 @@ void vgpu_init_mm_ops(struct gpu_ops *gops)
         gops->mm.l2_flush = vgpu_mm_l2_flush;
         gops->fb.tlb_invalidate = vgpu_mm_tlb_invalidate;
         gops->mm.get_physical_addr_bits = gk20a_mm_get_physical_addr_bits;
-        gops->mm.get_iova_addr = gk20a_mm_iova_addr;
+        gops->mm.gpu_phys_addr = gm20b_gpu_phys_addr;
         gops->mm.init_mm_setup_hw = NULL;
 }