diff options
author | Vaibhav Kachore <vkachore@nvidia.com> | 2018-03-14 06:44:20 -0400 |
---|---|---|
committer | Tejal Kudav <tkudav@nvidia.com> | 2018-06-14 09:44:08 -0400 |
commit | 1af9692e47f0f7c2a2f041d0075aa2651bd3995b (patch) | |
tree | 87227482805cd193f3773d982e5e145b58a7dd25 /drivers/gpu/nvgpu/vgpu | |
parent | ca3215c6b23c7d855ced899d8090aaa8ce9a9fa3 (diff) |
gpu: nvgpu: vgpu: add support for FECS VA
Enable FECS trace support for t194 Linux + HV
EVLR-2309
Change-Id: If22c931a54833eb995710b6e0dcad335e4ffbae6
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1674970
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nirav Patel <nipatel@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gr_vgpu.c | 36 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 21 |
2 files changed, 46 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c index 2ae615bf..83d27f17 100644 --- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c | |||
@@ -35,6 +35,7 @@ | |||
35 | #include "gk20a/dbg_gpu_gk20a.h" | 35 | #include "gk20a/dbg_gpu_gk20a.h" |
36 | #include "gk20a/channel_gk20a.h" | 36 | #include "gk20a/channel_gk20a.h" |
37 | #include "gk20a/tsg_gk20a.h" | 37 | #include "gk20a/tsg_gk20a.h" |
38 | #include "gk20a/fecs_trace_gk20a.h" | ||
38 | 39 | ||
39 | #include <nvgpu/hw/gk20a/hw_gr_gk20a.h> | 40 | #include <nvgpu/hw/gk20a/hw_gr_gk20a.h> |
40 | #include <nvgpu/hw/gk20a/hw_ctxsw_prog_gk20a.h> | 41 | #include <nvgpu/hw/gk20a/hw_ctxsw_prog_gk20a.h> |
@@ -122,6 +123,9 @@ int vgpu_gr_init_ctx_state(struct gk20a *g) | |||
122 | 123 | ||
123 | gr->ctx_vars.buffer_size = g->gr.ctx_vars.golden_image_size; | 124 | gr->ctx_vars.buffer_size = g->gr.ctx_vars.golden_image_size; |
124 | g->gr.ctx_vars.priv_access_map_size = 512 * 1024; | 125 | g->gr.ctx_vars.priv_access_map_size = 512 * 1024; |
126 | #ifdef CONFIG_GK20A_CTXSW_TRACE | ||
127 | g->gr.ctx_vars.fecs_trace_buffer_size = gk20a_fecs_trace_buffer_size(g); | ||
128 | #endif | ||
125 | return 0; | 129 | return 0; |
126 | } | 130 | } |
127 | 131 | ||
@@ -153,7 +157,12 @@ static int vgpu_gr_alloc_global_ctx_buffers(struct gk20a *g) | |||
153 | gr->ctx_vars.priv_access_map_size); | 157 | gr->ctx_vars.priv_access_map_size); |
154 | gr->global_ctx_buffer[PRIV_ACCESS_MAP].mem.size = | 158 | gr->global_ctx_buffer[PRIV_ACCESS_MAP].mem.size = |
155 | gr->ctx_vars.priv_access_map_size; | 159 | gr->ctx_vars.priv_access_map_size; |
156 | 160 | #ifdef CONFIG_GK20A_CTXSW_TRACE | |
161 | nvgpu_log_info(g, "fecs_trace_buffer_size : %d", | ||
162 | gr->ctx_vars.fecs_trace_buffer_size); | ||
163 | gr->global_ctx_buffer[FECS_TRACE_BUFFER].mem.size = | ||
164 | gr->ctx_vars.fecs_trace_buffer_size; | ||
165 | #endif | ||
157 | return 0; | 166 | return 0; |
158 | } | 167 | } |
159 | 168 | ||
@@ -219,6 +228,19 @@ static int vgpu_gr_map_global_ctx_buffers(struct gk20a *g, | |||
219 | g_bfr_size[PRIV_ACCESS_MAP_VA] = | 228 | g_bfr_size[PRIV_ACCESS_MAP_VA] = |
220 | gr->global_ctx_buffer[PRIV_ACCESS_MAP].mem.size; | 229 | gr->global_ctx_buffer[PRIV_ACCESS_MAP].mem.size; |
221 | 230 | ||
231 | /* FECS trace Buffer */ | ||
232 | #ifdef CONFIG_GK20A_CTXSW_TRACE | ||
233 | gpu_va = __nvgpu_vm_alloc_va(ch_vm, | ||
234 | gr->global_ctx_buffer[FECS_TRACE_BUFFER].mem.size, | ||
235 | gmmu_page_size_kernel); | ||
236 | |||
237 | if (!gpu_va) | ||
238 | goto clean_up; | ||
239 | |||
240 | g_bfr_va[FECS_TRACE_BUFFER_VA] = gpu_va; | ||
241 | g_bfr_size[FECS_TRACE_BUFFER_VA] = | ||
242 | gr->global_ctx_buffer[FECS_TRACE_BUFFER].mem.size; | ||
243 | #endif | ||
222 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_MAP_GR_GLOBAL_CTX; | 244 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_MAP_GR_GLOBAL_CTX; |
223 | msg.handle = vgpu_get_handle(g); | 245 | msg.handle = vgpu_get_handle(g); |
224 | p->handle = c->virt_ctx; | 246 | p->handle = c->virt_ctx; |
@@ -226,6 +248,9 @@ static int vgpu_gr_map_global_ctx_buffers(struct gk20a *g, | |||
226 | p->attr_va = g_bfr_va[ATTRIBUTE_VA]; | 248 | p->attr_va = g_bfr_va[ATTRIBUTE_VA]; |
227 | p->page_pool_va = g_bfr_va[PAGEPOOL_VA]; | 249 | p->page_pool_va = g_bfr_va[PAGEPOOL_VA]; |
228 | p->priv_access_map_va = g_bfr_va[PRIV_ACCESS_MAP_VA]; | 250 | p->priv_access_map_va = g_bfr_va[PRIV_ACCESS_MAP_VA]; |
251 | #ifdef CONFIG_GK20A_CTXSW_TRACE | ||
252 | p->fecs_trace_va = g_bfr_va[FECS_TRACE_BUFFER_VA]; | ||
253 | #endif | ||
229 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | 254 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); |
230 | if (err || msg.ret) | 255 | if (err || msg.ret) |
231 | goto clean_up; | 256 | goto clean_up; |
@@ -576,6 +601,15 @@ int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags) | |||
576 | nvgpu_err(g, "fail to commit gr ctx buffer"); | 601 | nvgpu_err(g, "fail to commit gr ctx buffer"); |
577 | goto out; | 602 | goto out; |
578 | } | 603 | } |
604 | #ifdef CONFIG_GK20A_CTXSW_TRACE | ||
605 | /* for fecs bind channel */ | ||
606 | err = gr_gk20a_elpg_protected_call(g, | ||
607 | vgpu_gr_load_golden_ctx_image(g, c)); | ||
608 | if (err) { | ||
609 | nvgpu_err(g, "fail to load golden ctx image"); | ||
610 | goto out; | ||
611 | } | ||
612 | #endif | ||
579 | } | 613 | } |
580 | 614 | ||
581 | /* PM ctxt switch is off by default */ | 615 | /* PM ctxt switch is off by default */ |
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index f81e8503..c6a6eae9 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -439,20 +439,21 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
439 | }, | 439 | }, |
440 | #ifdef CONFIG_GK20A_CTXSW_TRACE | 440 | #ifdef CONFIG_GK20A_CTXSW_TRACE |
441 | .fecs_trace = { | 441 | .fecs_trace = { |
442 | .alloc_user_buffer = NULL, | 442 | .alloc_user_buffer = vgpu_alloc_user_buffer, |
443 | .free_user_buffer = NULL, | 443 | .free_user_buffer = vgpu_free_user_buffer, |
444 | .mmap_user_buffer = NULL, | 444 | .mmap_user_buffer = vgpu_mmap_user_buffer, |
445 | .init = NULL, | 445 | .init = vgpu_fecs_trace_init, |
446 | .deinit = NULL, | 446 | .deinit = vgpu_fecs_trace_deinit, |
447 | .enable = NULL, | 447 | .enable = vgpu_fecs_trace_enable, |
448 | .disable = NULL, | 448 | .disable = vgpu_fecs_trace_disable, |
449 | .is_enabled = NULL, | 449 | .is_enabled = vgpu_fecs_trace_is_enabled, |
450 | .reset = NULL, | 450 | .reset = NULL, |
451 | .flush = NULL, | 451 | .flush = NULL, |
452 | .poll = NULL, | 452 | .poll = vgpu_fecs_trace_poll, |
453 | .bind_channel = NULL, | 453 | .bind_channel = NULL, |
454 | .unbind_channel = NULL, | 454 | .unbind_channel = NULL, |
455 | .max_entries = NULL, | 455 | .max_entries = vgpu_fecs_trace_max_entries, |
456 | .set_filter = vgpu_fecs_trace_set_filter, | ||
456 | }, | 457 | }, |
457 | #endif /* CONFIG_GK20A_CTXSW_TRACE */ | 458 | #endif /* CONFIG_GK20A_CTXSW_TRACE */ |
458 | .mm = { | 459 | .mm = { |