diff options
author | Richard Zhao <rizhao@nvidia.com> | 2016-08-12 20:10:28 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2016-08-18 18:03:54 -0400 |
commit | 198b895a881ca067a2411b7367579cb1d594ab5a (patch) | |
tree | 90e667382a589de9ba4d97bf511ca6bd42efe03c /drivers/gpu/nvgpu/vgpu | |
parent | deffbf8ee2017d4ea804f35946673dd0f6e0fcf2 (diff) |
gpu: nvgpu: use force_reset_ch in ch wdt handler
- let force_reset_ch pass down err code
- force_reset_ch callback can cover vgpu too.
Bug 1776876
JIRA VFND-2151
Change-Id: I48f7890294c6455247198e0cab5f21f83f61f0e1
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1202255
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index 9a8c319b..90e44e8c 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | |||
@@ -634,7 +634,8 @@ static int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice) | |||
634 | return err ? err : msg.ret; | 634 | return err ? err : msg.ret; |
635 | } | 635 | } |
636 | 636 | ||
637 | static int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch, bool verbose) | 637 | static int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch, |
638 | u32 err_code, bool verbose) | ||
638 | { | 639 | { |
639 | struct tsg_gk20a *tsg = NULL; | 640 | struct tsg_gk20a *tsg = NULL; |
640 | struct channel_gk20a *ch_tsg = NULL; | 641 | struct channel_gk20a *ch_tsg = NULL; |
@@ -653,16 +654,14 @@ static int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch, bool verbose) | |||
653 | 654 | ||
654 | list_for_each_entry(ch_tsg, &tsg->ch_list, ch_entry) { | 655 | list_for_each_entry(ch_tsg, &tsg->ch_list, ch_entry) { |
655 | if (gk20a_channel_get(ch_tsg)) { | 656 | if (gk20a_channel_get(ch_tsg)) { |
656 | gk20a_set_error_notifier(ch_tsg, | 657 | gk20a_set_error_notifier(ch_tsg, err_code); |
657 | NVGPU_CHANNEL_RESETCHANNEL_VERIF_ERROR); | ||
658 | gk20a_channel_put(ch_tsg); | 658 | gk20a_channel_put(ch_tsg); |
659 | } | 659 | } |
660 | } | 660 | } |
661 | 661 | ||
662 | mutex_unlock(&tsg->ch_list_lock); | 662 | mutex_unlock(&tsg->ch_list_lock); |
663 | } else { | 663 | } else { |
664 | gk20a_set_error_notifier(ch, | 664 | gk20a_set_error_notifier(ch, err_code); |
665 | NVGPU_CHANNEL_RESETCHANNEL_VERIF_ERROR); | ||
666 | } | 665 | } |
667 | 666 | ||
668 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET; | 667 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET; |