diff options
| author | Alex Frid <afrid@nvidia.com> | 2014-11-05 21:11:14 -0500 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:12:08 -0400 |
| commit | a612dc0dbd1a59632d119151c622a632e4edcee3 (patch) | |
| tree | 8e16fd19efc17e37da8b168dd5f20e246ba4287c /drivers/gpu/nvgpu/vgpu/vgpu.h | |
| parent | 4c021b1dfbb5e422d82370087f0813997e864f00 (diff) | |
dvfs: tegra21: Don't allow NA mode on certain parts
GM20b GPCPLL NA mode should not be enabled on Tegra21 parts with
speedo revision 0 or 1, even when CONFIG_TEGRA_USE_NA_GPCPLL is set.
Respectively, in this case non-NA GPU DVFS table must be selected.
To accommodate this restriction added GPU speedo id 1, and mapped
parts with revision 2 and above to this new speedo id. Kept speedo id
0 for parts with revision 0 or 1. Only non-NA DVFS table is selected
for speedo id 0. Either non-NA or NA mode DVFS table can be selected
by CONFIG_TEGRA_USE_NA_GPCPLL setting for parts with speedo id 1.
GM20b GPCPLL mode selection procedure is updated accordingly, so that
NA mode is disabled for speedo id 0, and selected for speedo id 1 by
CONFIG_TEGRA_USE_NA_GPCPLL. The latter takes precedence over GPCPLL
ADC calibration fuses - if config option is set, and part has speedo
id 1, NA mode is enabled even if calibration fuses are not burnt (less
accurate s/w self-calibration is used in this case).
Bug 1555318
Change-Id: I3948cb945206d0bc0f9f2bb6da5505c50ffc2af1
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/594718
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/vgpu.h')
0 files changed, 0 insertions, 0 deletions