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authorRichard Zhao <rizhao@nvidia.com>2016-05-23 21:35:34 -0400
committerTerje Bergstrom <tbergstrom@nvidia.com>2016-06-09 18:17:41 -0400
commit3735dba6f83e8de21eb2db620402d0ea9fd28835 (patch)
tree7b7b623c6c75824d769c28537ebfd1f6474182fc /drivers/gpu/nvgpu/vgpu/vgpu.c
parentc624f35383ab15f86d6a4ecac751d0836f154acf (diff)
gpu: nvgpu: vgpu: add general event support
Events like bpt int/pause will help cuda work properly. Bug 200173403 VFND-1568 Change-Id: I29e534969028bf08aedd81c99f5a536779f431d1 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1159621 (cherry picked from commit a266e53c514639e15ed166e2c8ce5a55efc48eda) Reviewed-on: http://git-master/r/1152154 Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/vgpu.c')
-rw-r--r--drivers/gpu/nvgpu/vgpu/vgpu.c34
1 files changed, 34 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.c b/drivers/gpu/nvgpu/vgpu/vgpu.c
index aa4ece5f..0d5dd27b 100644
--- a/drivers/gpu/nvgpu/vgpu/vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/vgpu.c
@@ -23,6 +23,8 @@
23#include "gk20a/hal_gk20a.h" 23#include "gk20a/hal_gk20a.h"
24#include "gk20a/hw_mc_gk20a.h" 24#include "gk20a/hw_mc_gk20a.h"
25#include "gk20a/ctxsw_trace_gk20a.h" 25#include "gk20a/ctxsw_trace_gk20a.h"
26#include "gk20a/tsg_gk20a.h"
27#include "gk20a/channel_gk20a.h"
26#include "gm20b/hal_gm20b.h" 28#include "gm20b/hal_gm20b.h"
27 29
28#ifdef CONFIG_ARCH_TEGRA_18x_SOC 30#ifdef CONFIG_ARCH_TEGRA_18x_SOC
@@ -97,6 +99,32 @@ int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value)
97 return 0; 99 return 0;
98} 100}
99 101
102static void vgpu_handle_general_event(struct gk20a *g,
103 struct tegra_vgpu_general_event_info *info)
104{
105 if (info->id >= g->fifo.num_channels ||
106 info->event_id >= NVGPU_IOCTL_CHANNEL_EVENT_ID_MAX) {
107 gk20a_err(g->dev, "invalid general event");
108 return;
109 }
110
111 if (info->is_tsg) {
112 struct tsg_gk20a *tsg = &g->fifo.tsg[info->id];
113
114 gk20a_tsg_event_id_post_event(tsg, info->event_id);
115 } else {
116 struct channel_gk20a *ch = &g->fifo.channel[info->id];
117
118 if (!gk20a_channel_get(ch)) {
119 gk20a_err(g->dev, "invalid channel %d for event %d",
120 (int)info->id, (int)info->event_id);
121 return;
122 }
123 gk20a_channel_event_id_post_event(ch, info->event_id);
124 gk20a_channel_put(ch);
125 }
126}
127
100static int vgpu_intr_thread(void *dev_id) 128static int vgpu_intr_thread(void *dev_id)
101{ 129{
102 struct gk20a *g = dev_id; 130 struct gk20a *g = dev_id;
@@ -127,6 +155,12 @@ static int vgpu_intr_thread(void *dev_id)
127 continue; 155 continue;
128 } 156 }
129 157
158 if (msg->event == TEGRA_VGPU_EVENT_CHANNEL) {
159 vgpu_handle_general_event(g, &msg->info.general_event);
160 tegra_gr_comm_release(handle);
161 continue;
162 }
163
130 if (msg->unit == TEGRA_VGPU_INTR_GR) 164 if (msg->unit == TEGRA_VGPU_INTR_GR)
131 vgpu_gr_isr(g, &msg->info.gr_intr); 165 vgpu_gr_isr(g, &msg->info.gr_intr);
132 else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_GR) 166 else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_GR)