gpu: nvgpu: vgpu: modify tsg enable sequence

TSG enable sequence in native has been modified due to a
hardware bug requiring enabling all channels with NEXT and
CTX_RELOAD set in a TSG, and then enabling rest of channels.
However it is not possible to check if NEXT and CTX_RELOAD
is set in vgpu. Have a separate implementation for enabling
tsg sequence in vgpu till the fix for hardware bug is
implemented for virtualized configuration.

Bug 200348087

Change-Id: I6bfc52138bc540c0ea0ad18a85155eeff6f9efa8
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1588740
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 13 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c b/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c
index 2be102e3..94d7140e 100644
--- a/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c
@@ -53,6 +53,19 @@ int vgpu_tsg_open(struct tsg_gk20a *tsg)
         return err;
 }
 
+int vgpu_enable_tsg(struct tsg_gk20a *tsg)
+{
+        struct gk20a *g = tsg->g;
+        struct channel_gk20a *ch;
+
+        nvgpu_rwsem_down_read(&tsg->ch_list_lock);
+        nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry)
+                g->ops.fifo.enable_channel(ch);
+        nvgpu_rwsem_up_read(&tsg->ch_list_lock);
+
+        return 0;
+}
+
 int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg,
                         struct channel_gk20a *ch)
 {