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authorPeter Daifuku <pdaifuku@nvidia.com>2017-10-06 19:27:14 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-10-13 18:20:18 -0400
commit57fb527a7e33384341fc18f1f918d5a8225057f5 (patch)
tree23bb49f879ac495834237c99564f0589d637f07e /drivers/gpu/nvgpu/vgpu/tsg_vgpu.c
parent3d343c9eeaa3415851d1c71b8815eb7dc2677b5a (diff)
gpu: nvgpu: vgpu: flatten out vgpu hal
Instead of calling the native HAL init function then adding multiple layers of modification for VGPU, flatten out the sequence so that all entry points are set statically and visible in a single file. JIRA ESRM-30 Change-Id: Ie424abb48bce5038874851d399baac5e4bb7d27c Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1574616 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/tsg_vgpu.c')
-rw-r--r--drivers/gpu/nvgpu/vgpu/tsg_vgpu.c17
1 files changed, 5 insertions, 12 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c b/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c
index 39d78983..2be102e3 100644
--- a/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c
@@ -27,10 +27,11 @@
27#include "gk20a/platform_gk20a.h" 27#include "gk20a/platform_gk20a.h"
28#include "gk20a/tsg_gk20a.h" 28#include "gk20a/tsg_gk20a.h"
29#include "vgpu.h" 29#include "vgpu.h"
30#include "fifo_vgpu.h"
30 31
31#include <nvgpu/bug.h> 32#include <nvgpu/bug.h>
32 33
33static int vgpu_tsg_open(struct tsg_gk20a *tsg) 34int vgpu_tsg_open(struct tsg_gk20a *tsg)
34{ 35{
35 struct tegra_vgpu_cmd_msg msg = {}; 36 struct tegra_vgpu_cmd_msg msg = {};
36 struct tegra_vgpu_tsg_open_params *p = 37 struct tegra_vgpu_tsg_open_params *p =
@@ -52,7 +53,7 @@ static int vgpu_tsg_open(struct tsg_gk20a *tsg)
52 return err; 53 return err;
53} 54}
54 55
55static int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg, 56int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg,
56 struct channel_gk20a *ch) 57 struct channel_gk20a *ch)
57{ 58{
58 struct tegra_vgpu_cmd_msg msg = {}; 59 struct tegra_vgpu_cmd_msg msg = {};
@@ -82,7 +83,7 @@ static int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg,
82 return err; 83 return err;
83} 84}
84 85
85static int vgpu_tsg_unbind_channel(struct channel_gk20a *ch) 86int vgpu_tsg_unbind_channel(struct channel_gk20a *ch)
86{ 87{
87 struct tegra_vgpu_cmd_msg msg = {}; 88 struct tegra_vgpu_cmd_msg msg = {};
88 struct tegra_vgpu_tsg_bind_unbind_channel_params *p = 89 struct tegra_vgpu_tsg_bind_unbind_channel_params *p =
@@ -105,7 +106,7 @@ static int vgpu_tsg_unbind_channel(struct channel_gk20a *ch)
105 return err; 106 return err;
106} 107}
107 108
108static int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice) 109int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice)
109{ 110{
110 struct tegra_vgpu_cmd_msg msg = {0}; 111 struct tegra_vgpu_cmd_msg msg = {0};
111 struct tegra_vgpu_tsg_timeslice_params *p = 112 struct tegra_vgpu_tsg_timeslice_params *p =
@@ -126,11 +127,3 @@ static int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice)
126 127
127 return err; 128 return err;
128} 129}
129
130void vgpu_init_tsg_ops(struct gpu_ops *gops)
131{
132 gops->fifo.tsg_bind_channel = vgpu_tsg_bind_channel;
133 gops->fifo.tsg_unbind_channel = vgpu_tsg_unbind_channel;
134 gops->fifo.tsg_set_timeslice = vgpu_tsg_set_timeslice;
135 gops->fifo.tsg_open = vgpu_tsg_open;
136}