gpu: nvgpu: vgpu: flatten out vgpu hal

Instead of calling the native HAL init function then adding
multiple layers of modification for VGPU, flatten out the sequence
so that all entry points are set statically and visible in a
single file.

JIRA ESRM-30

Change-Id: Ie424abb48bce5038874851d399baac5e4bb7d27c
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1574616
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 56 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/vgpu/mm_vgpu.h b/drivers/gpu/nvgpu/vgpu/mm_vgpu.h
new file mode 100644
index 00000000..ed66282c
--- /dev/null
+++ b/drivers/gpu/nvgpu/vgpu/mm_vgpu.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _MM_VGPU_H_
+#define _MM_VGPU_H_
+
+u64 vgpu_locked_gmmu_map(struct vm_gk20a *vm,
+                                u64 map_offset,
+                                struct nvgpu_sgt *sgt,
+                                u64 buffer_offset,
+                                u64 size,
+                                int pgsz_idx,
+                                u8 kind_v,
+                                u32 ctag_offset,
+                                u32 flags,
+                                int rw_flag,
+                                bool clear_ctags,
+                                bool sparse,
+                                bool priv,
+                                struct vm_gk20a_mapping_batch *batch,
+                                enum nvgpu_aperture aperture);
+void vgpu_locked_gmmu_unmap(struct vm_gk20a *vm,
+                                u64 vaddr,
+                                u64 size,
+                                int pgsz_idx,
+                                bool va_allocated,
+                                int rw_flag,
+                                bool sparse,
+                                struct vm_gk20a_mapping_batch *batch);
+int vgpu_vm_bind_channel(struct gk20a_as_share *as_share,
+                                struct channel_gk20a *ch);
+int vgpu_mm_fb_flush(struct gk20a *g);
+void vgpu_mm_l2_invalidate(struct gk20a *g);
+void vgpu_mm_l2_flush(struct gk20a *g, bool invalidate);
+void vgpu_mm_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb);
+void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable);
+#endif