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authorSami Kiminki <skiminki@nvidia.com>2015-05-22 13:48:22 -0400
committerTerje Bergstrom <tbergstrom@nvidia.com>2015-09-07 15:37:15 -0400
commiteade809c265ada214c6c47e1ad9db1706c868da0 (patch)
treea132050d7a4c2193f338e0082d258e1eac958cc1 /drivers/gpu/nvgpu/vgpu/mm_vgpu.c
parent57034b22ca17b217b683941dcebc0d69587d7d5e (diff)
gpu: nvgpu: Separate kernel and user GPU VA regions
Separate the kernel and userspace regions in the GPU virtual address space. Do this by reserving the last part of the GPU VA aperture for the kernel, and extend GPU VA aperture accordingly for regular address spaces. This prevents the kernel polluting the userspace-visible GPU VA regions, and thus, makes the success of fixed-address mapping more predictable. Bug 200077571 Change-Id: I63f0e73d4c815a4a9fa4a9ce568709974690ef0f Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: http://git-master/r/747191 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/mm_vgpu.c')
-rw-r--r--drivers/gpu/nvgpu/vgpu/mm_vgpu.c11
1 files changed, 7 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c
index c73037b6..2b23c4e6 100644
--- a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c
@@ -34,9 +34,12 @@ static int vgpu_init_mm_setup_sw(struct gk20a *g)
34 mm->g = g; 34 mm->g = g;
35 35
36 /*TBD: make channel vm size configurable */ 36 /*TBD: make channel vm size configurable */
37 mm->channel.size = 1ULL << NV_GMMU_VA_RANGE; 37 mm->channel.user_size = NV_MM_DEFAULT_USER_SIZE;
38 mm->channel.kernel_size = NV_MM_DEFAULT_KERNEL_SIZE;
38 39
39 gk20a_dbg_info("channel vm size: %dMB", (int)(mm->channel.size >> 20)); 40 gk20a_dbg_info("channel vm size: user %dMB kernel %dMB",
41 (int)(mm->channel.user_size >> 20),
42 (int)(mm->channel.kernel_size >> 20));
40 43
41 /* gk20a_init_gpu_characteristics expects this to be populated */ 44 /* gk20a_init_gpu_characteristics expects this to be populated */
42 vm->big_page_size = big_page_size; 45 vm->big_page_size = big_page_size;
@@ -276,8 +279,8 @@ static int vgpu_vm_alloc_share(struct gk20a_as_share *as_share,
276 vm->big_page_size = big_page_size; 279 vm->big_page_size = big_page_size;
277 280
278 vm->va_start = big_page_size << 10; /* create a one pde hole */ 281 vm->va_start = big_page_size << 10; /* create a one pde hole */
279 vm->va_limit = mm->channel.size; /* note this means channel.size is 282 vm->va_limit = mm->channel.user_size; /* note this means channel.size
280 really just the max */ 283 is really just the max */
281 284
282 msg.cmd = TEGRA_VGPU_CMD_AS_ALLOC_SHARE; 285 msg.cmd = TEGRA_VGPU_CMD_AS_ALLOC_SHARE;
283 msg.handle = platform->virt_handle; 286 msg.handle = platform->virt_handle;