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authorAparna Das <aparnad@nvidia.com>2018-07-06 13:45:53 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-07-09 19:36:17 -0400
commitad3b170f43dbd5ddb2698c5a193968ae1e584491 (patch)
treef27b4fd4c695920616ed360df5e95d9b46b88a95 /drivers/gpu/nvgpu/vgpu/gv11b
parent0ddd219697155bcb64aaa04544108519686e16cc (diff)
gpu: nvgpu: vgpu: ring doorbell after enabling TSG
In some use cases client will disable and preempt TSG and then re-enable it using IOCTLs provided In case there is only one context getting re-enabled and there is no other job submission in parallel runlist fetcher will just sleep until doorbell is received next time This causes above mentioned test cases to stall after re-enabling TSG until some one submits a new job and triggers a doorbell Fix this by explicitly triggering doorbell in vgpu code after we enable all channels in TSG. Bug 2205192 Change-Id: I25d643e06152adc6aaf874baf610316f6cd8f13f Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1772948 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/gv11b')
-rw-r--r--drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c2
-rw-r--r--drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.c20
-rw-r--r--drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.h2
3 files changed, 22 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
index 60beab9f..577c8f6e 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -380,7 +380,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
380 .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, 380 .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
381 .preempt_channel = vgpu_fifo_preempt_channel, 381 .preempt_channel = vgpu_fifo_preempt_channel,
382 .preempt_tsg = vgpu_fifo_preempt_tsg, 382 .preempt_tsg = vgpu_fifo_preempt_tsg,
383 .enable_tsg = vgpu_enable_tsg, 383 .enable_tsg = vgpu_gv11b_enable_tsg,
384 .disable_tsg = gk20a_disable_tsg, 384 .disable_tsg = gk20a_disable_tsg,
385 .tsg_verify_channel_status = NULL, 385 .tsg_verify_channel_status = NULL,
386 .tsg_verify_status_ctx_reload = NULL, 386 .tsg_verify_status_ctx_reload = NULL,
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.c
index 367c1299..e42bea1f 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.c
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.c
@@ -58,3 +58,23 @@ int vgpu_gv11b_tsg_bind_channel(struct tsg_gk20a *tsg,
58 58
59 return err; 59 return err;
60} 60}
61
62int vgpu_gv11b_enable_tsg(struct tsg_gk20a *tsg)
63{
64 struct gk20a *g = tsg->g;
65 struct channel_gk20a *ch;
66 struct channel_gk20a *last_ch = NULL;
67
68 nvgpu_rwsem_down_read(&tsg->ch_list_lock);
69 nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) {
70 g->ops.fifo.enable_channel(ch);
71 last_ch = ch;
72 }
73 nvgpu_rwsem_up_read(&tsg->ch_list_lock);
74
75 if (last_ch)
76 g->ops.fifo.ring_channel_doorbell(last_ch);
77
78 return 0;
79}
80
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.h b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.h
index 9ce84170..35eb6802 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.h
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.h
@@ -25,5 +25,5 @@
25 25
26int vgpu_gv11b_tsg_bind_channel(struct tsg_gk20a *tsg, 26int vgpu_gv11b_tsg_bind_channel(struct tsg_gk20a *tsg,
27 struct channel_gk20a *ch); 27 struct channel_gk20a *ch);
28 28int vgpu_gv11b_enable_tsg(struct tsg_gk20a *tsg);
29#endif 29#endif