gpu: nvgpu: vgpu: add basic t19x HALs

- Added t19x vgpu platform data
- Added basic vgpu HAL for gv11b.
- Added subctx header HAL.

Jira VFND-3796

Change-Id: I2b99364801b41d042b53e057f1a30e1194f354c3
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master/r/1474729
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 70 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c
new file mode 100644
index 00000000..93341427
--- /dev/null
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <gk20a/gk20a.h>
+#include <vgpu/vgpu.h>
+#include <linux/tegra_vgpu.h>
+
+int vgpu_gv11b_alloc_subctx_header(struct channel_gk20a *c)
+{
+        struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header;
+        struct tegra_vgpu_cmd_msg msg = {};
+        struct tegra_vgpu_alloc_ctx_header_params *p =
+                                &msg.params.t19x.alloc_ctx_header;
+        struct gr_gk20a *gr = &c->g->gr;
+        int err;
+
+        msg.cmd = TEGRA_VGPU_CMD_ALLOC_CTX_HEADER;
+        msg.handle = vgpu_get_handle(c->g);
+        p->ch_handle = c->virt_ctx;
+        p->ctx_header_va = __nvgpu_vm_alloc_va(c->vm,
+                                gr->ctx_vars.golden_image_size,
+                                gmmu_page_size_kernel);
+        if (!p->ctx_header_va) {
+                nvgpu_err(c->g, "alloc va failed for ctx_header");
+                return -ENOMEM;
+        }
+        err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
+        err = err ? err : msg.ret;
+        if (unlikely(err)) {
+                nvgpu_err(c->g, "alloc ctx_header failed err %d", err);
+                __nvgpu_vm_free_va(c->vm, p->ctx_header_va,
+                        gmmu_page_size_kernel);
+                return err;
+        }
+        ctx->mem.gpu_va = p->ctx_header_va;
+
+        return err;
+}
+
+void vgpu_gv11b_free_subctx_header(struct channel_gk20a *c)
+{
+        struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header;
+        struct tegra_vgpu_cmd_msg msg = {};
+        struct tegra_vgpu_free_ctx_header_params *p =
+                                &msg.params.t19x.free_ctx_header;
+        int err;
+
+        if (ctx->mem.gpu_va) {
+                msg.cmd = TEGRA_VGPU_CMD_FREE_CTX_HEADER;
+                msg.handle = vgpu_get_handle(c->g);
+                p->ch_handle = c->virt_ctx;
+                err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
+                err = err ? err : msg.ret;
+                if (unlikely(err))
+                        nvgpu_err(c->g, "free ctx_header failed err %d", err);
+                __nvgpu_vm_free_va(c->vm, ctx->mem.gpu_va,
+                                gmmu_page_size_kernel);
+                ctx->mem.gpu_va = 0;
+        }
+}