gpu: nvgpu: gv11b: use scg perf for smid numbering

For SCG to work, smid numbering needs to be done
based on scg performance of tpcs. For gv11b and
gv11b vgpu, reuse gv100 function "gr_gv100_init_sm_id_table"
to do this.

Used local variable "index" to avoid multiple computations in
the function: gr_gv100_init_sm_id_table
index = sm_id + sm

Add deug info for printing initialized gpc/tpc/sm/global_tpc
indexs.

Bug 1842197

Change-Id: Ibf10f47f10a8ca58b86c307a22e159b2cc0d0f43
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1583916
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 3 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
index 2cd8018c..7f6df820 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -74,6 +74,8 @@
 #include <gv11b/ltc_gv11b.h>
 #include <gv11b/gv11b_gating_reglist.h>
 
+#include <gv100/gr_gv100.h>
+
 #include <nvgpu/enabled.h>
 
 #include "vgpu_gr_gv11b.h"
@@ -180,7 +182,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
                 .resume_contexts = vgpu_gr_resume_contexts,
                 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
                 .fuse_override = gp10b_gr_fuse_override,
-                .init_sm_id_table = gr_gv11b_init_sm_id_table,
+                .init_sm_id_table = gr_gv100_init_sm_id_table,
                 .load_smid_config = gr_gv11b_load_smid_config,
                 .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering,
                 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,