diff options
author | Richard Zhao <rizhao@nvidia.com> | 2018-01-30 02:24:37 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-02-27 17:30:52 -0500 |
commit | 6393eddfa996fba03464f897b85aa5ec79860fed (patch) | |
tree | 557ebe9be93e2b0464118e7d8ec019d9d5dbae5f /drivers/gpu/nvgpu/vgpu/gr_vgpu.h | |
parent | 7932568b7fe9e16b2b83bc58b2b3686c0d5e52d4 (diff) |
gpu: nvgpu: vgpu: move common files out of linux folder
Most of files have been moved out of linux folder. More code could be
common as halifying going on.
Jira EVLR-2364
Change-Id: Ia9dbdbc82f45ceefe5c788eac7517000cd455d5e
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1649947
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/gr_vgpu.h')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gr_vgpu.h | 74 |
1 files changed, 74 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.h b/drivers/gpu/nvgpu/vgpu/gr_vgpu.h new file mode 100644 index 00000000..1f55823c --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.h | |||
@@ -0,0 +1,74 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef _GR_VGPU_H_ | ||
24 | #define _GR_VGPU_H_ | ||
25 | |||
26 | #include <nvgpu/types.h> | ||
27 | |||
28 | struct gk20a; | ||
29 | struct channel_gk20a; | ||
30 | struct gr_gk20a; | ||
31 | struct gr_zcull_info; | ||
32 | struct zbc_entry; | ||
33 | struct zbc_query_params; | ||
34 | struct dbg_session_gk20a; | ||
35 | struct tsg_gk20a; | ||
36 | |||
37 | void vgpu_gr_detect_sm_arch(struct gk20a *g); | ||
38 | void vgpu_gr_free_channel_ctx(struct channel_gk20a *c, bool is_tsg); | ||
39 | void vgpu_gr_free_tsg_ctx(struct tsg_gk20a *tsg); | ||
40 | int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags); | ||
41 | int vgpu_gr_bind_ctxsw_zcull(struct gk20a *g, struct gr_gk20a *gr, | ||
42 | struct channel_gk20a *c, u64 zcull_va, | ||
43 | u32 mode); | ||
44 | int vgpu_gr_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr, | ||
45 | struct gr_zcull_info *zcull_params); | ||
46 | u32 vgpu_gr_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); | ||
47 | u32 vgpu_gr_get_max_fbps_count(struct gk20a *g); | ||
48 | u32 vgpu_gr_get_fbp_en_mask(struct gk20a *g); | ||
49 | u32 vgpu_gr_get_max_ltc_per_fbp(struct gk20a *g); | ||
50 | u32 vgpu_gr_get_max_lts_per_ltc(struct gk20a *g); | ||
51 | u32 *vgpu_gr_rop_l2_en_mask(struct gk20a *g); | ||
52 | int vgpu_gr_add_zbc(struct gk20a *g, struct gr_gk20a *gr, | ||
53 | struct zbc_entry *zbc_val); | ||
54 | int vgpu_gr_query_zbc(struct gk20a *g, struct gr_gk20a *gr, | ||
55 | struct zbc_query_params *query_params); | ||
56 | int vgpu_gr_set_sm_debug_mode(struct gk20a *g, | ||
57 | struct channel_gk20a *ch, u64 sms, bool enable); | ||
58 | int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g, | ||
59 | struct channel_gk20a *ch, bool enable); | ||
60 | int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, | ||
61 | struct channel_gk20a *ch, bool enable); | ||
62 | int vgpu_gr_clear_sm_error_state(struct gk20a *g, | ||
63 | struct channel_gk20a *ch, u32 sm_id); | ||
64 | int vgpu_gr_suspend_contexts(struct gk20a *g, | ||
65 | struct dbg_session_gk20a *dbg_s, | ||
66 | int *ctx_resident_ch_fd); | ||
67 | int vgpu_gr_resume_contexts(struct gk20a *g, | ||
68 | struct dbg_session_gk20a *dbg_s, | ||
69 | int *ctx_resident_ch_fd); | ||
70 | int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va); | ||
71 | int vgpu_gr_init_sm_id_table(struct gk20a *g); | ||
72 | int vgpu_gr_init_fs_state(struct gk20a *g); | ||
73 | |||
74 | #endif | ||