gpu: nvgpu: vgpu: flatten out vgpu hal

Instead of calling the native HAL init function then adding
multiple layers of modification for VGPU, flatten out the sequence
so that all entry points are set statically and visible in a
single file.

JIRA ESRM-30

Change-Id: Ie424abb48bce5038874851d399baac5e4bb7d27c
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1574616
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 44 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.h b/drivers/gpu/nvgpu/vgpu/gr_vgpu.h
index b6df991e..5a5e0928 100644
--- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.h
+++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.h
@@ -23,6 +23,50 @@
 #ifndef _GR_VGPU_H_
 #define _GR_VGPU_H_
 
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct channel_gk20a;
+struct nvgpu_alloc_obj_ctx_args;
+struct gr_gk20a;
+struct gr_zcull_info;
+struct zbc_entry;
+struct zbc_query_params;
+struct dbg_session_gk20a;
+
+void vgpu_gr_detect_sm_arch(struct gk20a *g);
+void vgpu_gr_free_channel_ctx(struct channel_gk20a *c, bool is_tsg);
+int vgpu_gr_alloc_obj_ctx(struct channel_gk20a  *c,
+                                struct nvgpu_alloc_obj_ctx_args *args);
+int vgpu_gr_bind_ctxsw_zcull(struct gk20a *g, struct gr_gk20a *gr,
+                                struct channel_gk20a *c, u64 zcull_va,
+                                u32 mode);
+int vgpu_gr_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr,
+                                struct gr_zcull_info *zcull_params);
+u32 vgpu_gr_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index);
+u32 vgpu_gr_get_max_fbps_count(struct gk20a *g);
+u32 vgpu_gr_get_fbp_en_mask(struct gk20a *g);
+u32 vgpu_gr_get_max_ltc_per_fbp(struct gk20a *g);
+u32 vgpu_gr_get_max_lts_per_ltc(struct gk20a *g);
+u32 *vgpu_gr_rop_l2_en_mask(struct gk20a *g);
+int vgpu_gr_add_zbc(struct gk20a *g, struct gr_gk20a *gr,
+                           struct zbc_entry *zbc_val);
+int vgpu_gr_query_zbc(struct gk20a *g, struct gr_gk20a *gr,
+                        struct zbc_query_params *query_params);
+int vgpu_gr_set_sm_debug_mode(struct gk20a *g,
+        struct channel_gk20a *ch, u64 sms, bool enable);
+int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g,
+        struct channel_gk20a *ch, bool enable);
+int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g,
+        struct channel_gk20a *ch, bool enable);
+int vgpu_gr_clear_sm_error_state(struct gk20a *g,
+                struct channel_gk20a *ch, u32 sm_id);
+int vgpu_gr_suspend_contexts(struct gk20a *g,
+                struct dbg_session_gk20a *dbg_s,
+                int *ctx_resident_ch_fd);
+int vgpu_gr_resume_contexts(struct gk20a *g,
+                struct dbg_session_gk20a *dbg_s,
+                int *ctx_resident_ch_fd);
 int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va);
 
 #endif