diff options
author | Richard Zhao <rizhao@nvidia.com> | 2015-07-23 18:10:42 -0400 |
---|---|---|
committer | Richard Zhao <rizhao@nvidia.com> | 2015-08-19 08:12:00 -0400 |
commit | a88e58cc9d2c4b9f852716240b3cabc9449d8679 (patch) | |
tree | 5965b2645913695ed36e61aa4c42fdb60045cf42 /drivers/gpu/nvgpu/vgpu/gr_vgpu.c | |
parent | db8bce518bcf2a1b46e5897f55469f348a16c9a2 (diff) |
gpu: nvgpu: vgpu: add t210 gm20b support
- add hal initializaiton
- create folders vgpu/gk20a and vgpu/gm20b for specific code
Bug 1653185
Change-Id: If94d45e22a1d73d2e4916673736cc29751be4e40
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/774148
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-by: Ken Adams <kadams@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/gr_vgpu.c')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gr_vgpu.c | 68 |
1 files changed, 43 insertions, 25 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c index 99754cae..60a8f6c5 100644 --- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c | |||
@@ -601,36 +601,18 @@ static int vgpu_gr_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr, | |||
601 | return 0; | 601 | return 0; |
602 | } | 602 | } |
603 | 603 | ||
604 | static void vgpu_gr_detect_sm_arch(struct gk20a *g) | 604 | static u32 vgpu_gr_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) |
605 | { | 605 | { |
606 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); | 606 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); |
607 | u32 v = 0, raw_version, version = 0; | 607 | u32 data; |
608 | 608 | ||
609 | gk20a_dbg_fn(""); | 609 | WARN_ON(gpc_index > 0); |
610 | 610 | ||
611 | if (vgpu_get_attribute(platform->virt_handle, | 611 | if (vgpu_get_attribute(platform->virt_handle, |
612 | TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH, &v)) | 612 | TEGRA_VGPU_ATTRIB_GPC0_TPC_MASK, &data)) |
613 | gk20a_err(dev_from_gk20a(g), "failed to retrieve SM arch"); | 613 | gk20a_err(dev_from_gk20a(g), "failed to retrieve gpc0_tpc_mask"); |
614 | |||
615 | raw_version = gr_gpc0_tpc0_sm_arch_spa_version_v(v); | ||
616 | if (raw_version == gr_gpc0_tpc0_sm_arch_spa_version_smkepler_lp_v()) | ||
617 | version = 0x320; /* SM 3.2 */ | ||
618 | else | ||
619 | gk20a_err(dev_from_gk20a(g), "Unknown SM version 0x%x", | ||
620 | raw_version); | ||
621 | |||
622 | /* on Kepler, SM version == SPA version */ | ||
623 | g->gpu_characteristics.sm_arch_spa_version = version; | ||
624 | g->gpu_characteristics.sm_arch_sm_version = version; | ||
625 | |||
626 | g->gpu_characteristics.sm_arch_warp_count = | ||
627 | gr_gpc0_tpc0_sm_arch_warp_count_v(v); | ||
628 | } | ||
629 | 614 | ||
630 | static u32 vgpu_gr_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | 615 | return data; |
631 | { | ||
632 | /* One TPC for gk20a */ | ||
633 | return 0x1; | ||
634 | } | 616 | } |
635 | 617 | ||
636 | static u32 vgpu_gr_get_max_fbps_count(struct gk20a *g) | 618 | static u32 vgpu_gr_get_max_fbps_count(struct gk20a *g) |
@@ -661,6 +643,40 @@ static u32 vgpu_gr_get_fbp_en_mask(struct gk20a *g) | |||
661 | return fbp_en_mask; | 643 | return fbp_en_mask; |
662 | } | 644 | } |
663 | 645 | ||
646 | static u32 vgpu_gr_get_max_ltc_per_fbp(struct gk20a *g) | ||
647 | { | ||
648 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); | ||
649 | u32 val = 0; | ||
650 | |||
651 | gk20a_dbg_fn(""); | ||
652 | |||
653 | if (vgpu_get_attribute(platform->virt_handle, | ||
654 | TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP, &val)) | ||
655 | gk20a_err(dev_from_gk20a(g), "failed to retrieve max ltc per fbp"); | ||
656 | |||
657 | return val; | ||
658 | } | ||
659 | |||
660 | static u32 vgpu_gr_get_max_lts_per_ltc(struct gk20a *g) | ||
661 | { | ||
662 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); | ||
663 | u32 val = 0; | ||
664 | |||
665 | gk20a_dbg_fn(""); | ||
666 | |||
667 | if (vgpu_get_attribute(platform->virt_handle, | ||
668 | TEGRA_VGPU_ATTRIB_MAX_LTS_PER_LTC, &val)) | ||
669 | gk20a_err(dev_from_gk20a(g), "failed to retrieve lts per ltc"); | ||
670 | |||
671 | return val; | ||
672 | } | ||
673 | |||
674 | static u32 *vgpu_gr_rop_l2_en_mask(struct gk20a *g) | ||
675 | { | ||
676 | /* no one use it yet */ | ||
677 | return NULL; | ||
678 | } | ||
679 | |||
664 | static int vgpu_gr_add_zbc(struct gk20a *g, struct gr_gk20a *gr, | 680 | static int vgpu_gr_add_zbc(struct gk20a *g, struct gr_gk20a *gr, |
665 | struct zbc_entry *zbc_val) | 681 | struct zbc_entry *zbc_val) |
666 | { | 682 | { |
@@ -875,10 +891,12 @@ void vgpu_init_gr_ops(struct gpu_ops *gops) | |||
875 | gops->gr.free_obj_ctx = vgpu_gr_free_obj_ctx; | 891 | gops->gr.free_obj_ctx = vgpu_gr_free_obj_ctx; |
876 | gops->gr.bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull; | 892 | gops->gr.bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull; |
877 | gops->gr.get_zcull_info = vgpu_gr_get_zcull_info; | 893 | gops->gr.get_zcull_info = vgpu_gr_get_zcull_info; |
878 | gops->gr.detect_sm_arch = vgpu_gr_detect_sm_arch; | ||
879 | gops->gr.get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask; | 894 | gops->gr.get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask; |
880 | gops->gr.get_max_fbps_count = vgpu_gr_get_max_fbps_count; | 895 | gops->gr.get_max_fbps_count = vgpu_gr_get_max_fbps_count; |
881 | gops->gr.get_fbp_en_mask = vgpu_gr_get_fbp_en_mask; | 896 | gops->gr.get_fbp_en_mask = vgpu_gr_get_fbp_en_mask; |
897 | gops->gr.get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp; | ||
898 | gops->gr.get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc; | ||
899 | gops->gr.get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask; | ||
882 | gops->gr.zbc_set_table = vgpu_gr_add_zbc; | 900 | gops->gr.zbc_set_table = vgpu_gr_add_zbc; |
883 | gops->gr.zbc_query_table = vgpu_gr_query_zbc; | 901 | gops->gr.zbc_query_table = vgpu_gr_query_zbc; |
884 | } | 902 | } |