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authorSam Payne <spayne@nvidia.com>2014-10-31 17:27:33 -0400
committerDan Willemsen <dwillemsen@nvidia.com>2015-03-18 15:11:56 -0400
commit8c6a9fd1151299697037d58f33cfa306d8ac5d87 (patch)
tree9bb909474f12565e7f61251b8b80f300030bde52 /drivers/gpu/nvgpu/vgpu/gr_vgpu.c
parent4f6dddcf78233b9939ee32c6f09519f27c3b8fb4 (diff)
Revert "gpu: nvgpu: GR and LTC HAL to use const structs"
This reverts commit 41b82e97164138f45fbdaef6ab6939d82ca9419e. Change-Id: Iabd01fcb124e0d22cd9be62151a6552cbb27fc94 Signed-off-by: Sam Payne <spayne@nvidia.com> Reviewed-on: http://git-master/r/592221 Tested-by: Hoang Pham <hopham@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Mitch Luban <mluban@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/gr_vgpu.c')
-rw-r--r--drivers/gpu/nvgpu/vgpu/gr_vgpu.c27
1 files changed, 11 insertions, 16 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
index 3e0f9dc3..6f8baa4b 100644
--- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
@@ -15,7 +15,6 @@
15 15
16#include "vgpu/vgpu.h" 16#include "vgpu/vgpu.h"
17#include "gk20a/hw_gr_gk20a.h" 17#include "gk20a/hw_gr_gk20a.h"
18#include "gr_ops.h"
19 18
20static int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va) 19static int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va)
21{ 20{
@@ -105,7 +104,7 @@ static int vgpu_gr_alloc_global_ctx_buffers(struct gk20a *g)
105 104
106 gk20a_dbg_fn(""); 105 gk20a_dbg_fn("");
107 106
108 attr_buffer_size = g->ops.gr->calc_global_ctx_buffer_size(g); 107 attr_buffer_size = g->ops.gr.calc_global_ctx_buffer_size(g);
109 108
110 gk20a_dbg_info("cb_buffer_size : %d", cb_buffer_size); 109 gk20a_dbg_info("cb_buffer_size : %d", cb_buffer_size);
111 gr->global_ctx_buffer[CIRCULAR].size = cb_buffer_size; 110 gr->global_ctx_buffer[CIRCULAR].size = cb_buffer_size;
@@ -398,7 +397,7 @@ static int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c,
398 return -EINVAL; 397 return -EINVAL;
399 } 398 }
400 399
401 if (!g->ops.gr->is_valid_class(g, args->class_num)) { 400 if (!g->ops.gr.is_valid_class(g, args->class_num)) {
402 gk20a_err(dev_from_gk20a(g), 401 gk20a_err(dev_from_gk20a(g),
403 "invalid obj class 0x%x", args->class_num); 402 "invalid obj class 0x%x", args->class_num);
404 err = -EINVAL; 403 err = -EINVAL;
@@ -525,9 +524,9 @@ static int vgpu_gr_init_gr_config(struct gk20a *g, struct gr_gk20a *gr)
525 &gr->max_tpc_count)) 524 &gr->max_tpc_count))
526 return -ENOMEM; 525 return -ENOMEM;
527 526
528 g->ops.gr->bundle_cb_defaults(g); 527 g->ops.gr.bundle_cb_defaults(g);
529 g->ops.gr->cb_size_default(g); 528 g->ops.gr.cb_size_default(g);
530 g->ops.gr->calc_global_ctx_buffer_size(g); 529 g->ops.gr.calc_global_ctx_buffer_size(g);
531 return 0; 530 return 0;
532} 531}
533 532
@@ -613,7 +612,7 @@ static int vgpu_gr_init_gr_setup_sw(struct gk20a *g)
613 if (err) 612 if (err)
614 goto clean_up; 613 goto clean_up;
615 614
616 err = g->ops.ltc->init_comptags(g, gr); 615 err = g->ops.ltc.init_comptags(g, gr);
617 if (err) 616 if (err)
618 goto clean_up; 617 goto clean_up;
619 618
@@ -678,15 +677,11 @@ int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info)
678 return 0; 677 return 0;
679} 678}
680 679
681static struct gpu_gr_ops vgpu_gr_ops = {
682 .free_channel_ctx = vgpu_gr_free_channel_ctx,
683 .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx,
684 .free_obj_ctx = vgpu_gr_free_obj_ctx,
685 .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull,
686 .get_zcull_info = vgpu_gr_get_zcull_info,
687};
688
689void vgpu_init_gr_ops(struct gpu_ops *gops) 680void vgpu_init_gr_ops(struct gpu_ops *gops)
690{ 681{
691 gops->gr = &vgpu_gr_ops; 682 gops->gr.free_channel_ctx = vgpu_gr_free_channel_ctx;
683 gops->gr.alloc_obj_ctx = vgpu_gr_alloc_obj_ctx;
684 gops->gr.free_obj_ctx = vgpu_gr_free_obj_ctx;
685 gops->gr.bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull;
686 gops->gr.get_zcull_info = vgpu_gr_get_zcull_info;
692} 687}