Merge remote-tracking branch 'remotes/origin/dev/merge-nvgpu-t18x-into-nvgpu' into dev-kernel

Merge T186 - gp10b/gp106 code into common nvgpu repo

Bug 200266498

Change-Id: Ibf100ee38010cbed85c149b69b99147256f9a005
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>

7 files changed, 656 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c
new file mode 100644
index 00000000..23d945fb
--- /dev/null
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2015-2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "vgpu_fifo_gp10b.h"
+
+static int vgpu_gp10b_fifo_init_engine_info(struct fifo_gk20a *f)
+{
+        struct fifo_engine_info_gk20a *gr_info;
+        struct fifo_engine_info_gk20a *ce_info;
+        const u32 gr_sw_id = ENGINE_GR_GK20A;
+        const u32 ce_sw_id = ENGINE_GRCE_GK20A;
+
+        gk20a_dbg_fn("");
+
+        f->num_engines = 2;
+
+        gr_info = &f->engine_info[0];
+
+        /* FIXME: retrieve this from server */
+        gr_info->runlist_id = 0;
+        gr_info->engine_enum = gr_sw_id;
+        f->active_engines_list[0] = 0;
+
+        ce_info = &f->engine_info[1];
+        ce_info->runlist_id = 0;
+        ce_info->inst_id = 0;
+        ce_info->engine_enum = ce_sw_id;
+        f->active_engines_list[1] = 1;
+
+        return 0;
+}
+
+void vgpu_gp10b_init_fifo_ops(struct gpu_ops *gops)
+{
+        /* syncpoint protection not supported yet */
+        gops->fifo.init_engine_info = vgpu_gp10b_fifo_init_engine_info;
+        gops->fifo.resetup_ramfc = NULL;
+}
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h
new file mode 100644
index 00000000..4ede0b6d
--- /dev/null
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef __VGPU_FIFO_GP10B_H__
+#define __VGPU_FIFO_GP10B_H__
+
+#include "gk20a/gk20a.h"
+
+void vgpu_gp10b_init_fifo_ops(struct gpu_ops *gops);
+
+#endif
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
new file mode 100644
index 00000000..85dc8c22
--- /dev/null
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
@@ -0,0 +1,321 @@
+/*
+ * Copyright (c) 2015-2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "vgpu/vgpu.h"
+#include "vgpu_gr_gp10b.h"
+#include "vgpu/gm20b/vgpu_gr_gm20b.h"
+
+#include "gp10b/hw_gr_gp10b.h"
+
+static void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
+                                struct gr_ctx_desc *gr_ctx)
+{
+        struct tegra_vgpu_cmd_msg msg = {0};
+        struct tegra_vgpu_gr_ctx_params *p = &msg.params.gr_ctx;
+        int err;
+
+        gk20a_dbg_fn("");
+
+        if (!gr_ctx || !gr_ctx->mem.gpu_va)
+                return;
+
+        msg.cmd = TEGRA_VGPU_CMD_GR_CTX_FREE;
+        msg.handle = vgpu_get_handle(g);
+        p->gr_ctx_handle = gr_ctx->virt_ctx;
+        err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
+        WARN_ON(err || msg.ret);
+
+        gk20a_vm_free_va(vm, gr_ctx->mem.gpu_va, gr_ctx->mem.size,
+                        gmmu_page_size_kernel);
+
+        gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.pagepool_ctxsw_buffer);
+        gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer);
+        gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer);
+        gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer);
+
+        kfree(gr_ctx);
+}
+
+static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g,
+                                struct gr_ctx_desc **__gr_ctx,
+                                struct vm_gk20a *vm,
+                                u32 class,
+                                u32 flags)
+{
+        struct gr_ctx_desc *gr_ctx;
+        u32 graphics_preempt_mode = 0;
+        u32 compute_preempt_mode = 0;
+        int err;
+
+        gk20a_dbg_fn("");
+
+        err = vgpu_gr_alloc_gr_ctx(g, __gr_ctx, vm, class, flags);
+        if (err)
+                return err;
+
+        gr_ctx = *__gr_ctx;
+
+        if (flags & NVGPU_ALLOC_OBJ_FLAGS_GFXP)
+                graphics_preempt_mode = NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP;
+        if (flags & NVGPU_ALLOC_OBJ_FLAGS_CILP)
+                compute_preempt_mode = NVGPU_COMPUTE_PREEMPTION_MODE_CILP;
+
+        if (graphics_preempt_mode || compute_preempt_mode) {
+                if (g->ops.gr.set_ctxsw_preemption_mode) {
+                        err = g->ops.gr.set_ctxsw_preemption_mode(g, gr_ctx, vm,
+                            class, graphics_preempt_mode, compute_preempt_mode);
+                        if (err) {
+                                gk20a_err(dev_from_gk20a(g),
+                                        "set_ctxsw_preemption_mode failed");
+                                goto fail;
+                        }
+                } else {
+                        err = -ENOSYS;
+                        goto fail;
+                }
+        }
+
+        gk20a_dbg_fn("done");
+        return err;
+
+fail:
+        vgpu_gr_gp10b_free_gr_ctx(g, vm, gr_ctx);
+        return err;
+}
+
+static int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
+                                struct gr_ctx_desc *gr_ctx,
+                                struct vm_gk20a *vm, u32 class,
+                                u32 graphics_preempt_mode,
+                                u32 compute_preempt_mode)
+{
+        struct tegra_vgpu_cmd_msg msg = {};
+        struct tegra_vgpu_gr_bind_ctxsw_buffers_params *p =
+                                &msg.params.gr_bind_ctxsw_buffers;
+        int err = 0;
+
+        WARN_ON(TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAX !=
+                TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_LAST);
+
+        if (class == PASCAL_A && g->gr.t18x.ctx_vars.force_preemption_gfxp)
+                graphics_preempt_mode = NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP;
+
+        if (class == PASCAL_COMPUTE_A &&
+                        g->gr.t18x.ctx_vars.force_preemption_cilp)
+                compute_preempt_mode = NVGPU_COMPUTE_PREEMPTION_MODE_CILP;
+
+        /* check for invalid combinations */
+        if ((graphics_preempt_mode == 0) && (compute_preempt_mode == 0))
+                return -EINVAL;
+
+        if ((graphics_preempt_mode == NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP) &&
+                   (compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CILP))
+                return -EINVAL;
+
+        /* set preemption modes */
+        switch (graphics_preempt_mode) {
+        case NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP:
+        {
+                u32 spill_size =
+                        gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() *
+                        gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v();
+                u32 pagepool_size = g->ops.gr.pagepool_default_size(g) *
+                        gr_scc_pagepool_total_pages_byte_granularity_v();
+                u32 betacb_size = g->gr.attrib_cb_default_size +
+                                  (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() -
+                                   gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v());
+                u32 attrib_cb_size = (betacb_size + g->gr.alpha_cb_size) *
+                                  gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() *
+                                  g->gr.max_tpc_count;
+                struct mem_desc *desc;
+
+                attrib_cb_size = ALIGN(attrib_cb_size, 128);
+
+                gk20a_dbg_info("gfxp context preempt size=%d",
+                        g->gr.t18x.ctx_vars.preempt_image_size);
+                gk20a_dbg_info("gfxp context spill size=%d", spill_size);
+                gk20a_dbg_info("gfxp context pagepool size=%d", pagepool_size);
+                gk20a_dbg_info("gfxp context attrib cb size=%d",
+                        attrib_cb_size);
+
+                err = gr_gp10b_alloc_buffer(vm,
+                                        g->gr.t18x.ctx_vars.preempt_image_size,
+                                        &gr_ctx->t18x.preempt_ctxsw_buffer);
+                if (err) {
+                        err = -ENOMEM;
+                        goto fail;
+                }
+                desc = &gr_ctx->t18x.preempt_ctxsw_buffer;
+                p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->gpu_va;
+                p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->size;
+
+                err = gr_gp10b_alloc_buffer(vm,
+                                        spill_size,
+                                        &gr_ctx->t18x.spill_ctxsw_buffer);
+                if (err) {
+                        err = -ENOMEM;
+                        goto fail;
+                }
+                desc = &gr_ctx->t18x.spill_ctxsw_buffer;
+                p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->gpu_va;
+                p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->size;
+
+                err = gr_gp10b_alloc_buffer(vm,
+                                        pagepool_size,
+                                        &gr_ctx->t18x.pagepool_ctxsw_buffer);
+                if (err) {
+                        err = -ENOMEM;
+                        goto fail;
+                }
+                desc = &gr_ctx->t18x.pagepool_ctxsw_buffer;
+                p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] =
+                        desc->gpu_va;
+                p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = desc->size;
+
+                err = gr_gp10b_alloc_buffer(vm,
+                                        attrib_cb_size,
+                                        &gr_ctx->t18x.betacb_ctxsw_buffer);
+                if (err) {
+                        err = -ENOMEM;
+                        goto fail;
+                }
+                desc = &gr_ctx->t18x.betacb_ctxsw_buffer;
+                p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] =
+                        desc->gpu_va;
+                p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = desc->size;
+
+                gr_ctx->graphics_preempt_mode = NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP;
+                p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_GFX_GFXP;
+                break;
+        }
+        case NVGPU_GRAPHICS_PREEMPTION_MODE_WFI:
+                gr_ctx->graphics_preempt_mode = graphics_preempt_mode;
+                break;
+
+        default:
+                break;
+        }
+
+        if (class == PASCAL_COMPUTE_A) {
+                switch (compute_preempt_mode) {
+                case NVGPU_COMPUTE_PREEMPTION_MODE_WFI:
+                        gr_ctx->compute_preempt_mode =
+                                NVGPU_COMPUTE_PREEMPTION_MODE_WFI;
+                        p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_WFI;
+                        break;
+                case NVGPU_COMPUTE_PREEMPTION_MODE_CTA:
+                        gr_ctx->compute_preempt_mode =
+                                NVGPU_COMPUTE_PREEMPTION_MODE_CTA;
+                        p->mode =
+                                TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CTA;
+                        break;
+                case NVGPU_COMPUTE_PREEMPTION_MODE_CILP:
+                        gr_ctx->compute_preempt_mode =
+                                NVGPU_COMPUTE_PREEMPTION_MODE_CILP;
+                        p->mode =
+                                TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CILP;
+                        break;
+                default:
+                        break;
+                }
+        }
+
+        if (gr_ctx->graphics_preempt_mode || gr_ctx->compute_preempt_mode) {
+                msg.cmd = TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS;
+                msg.handle = vgpu_get_handle(g);
+                p->gr_ctx_handle = gr_ctx->virt_ctx;
+                err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
+                if (err || msg.ret) {
+                        err = -ENOMEM;
+                        goto fail;
+                }
+        }
+
+        return err;
+
+fail:
+        gk20a_err(dev_from_gk20a(g), "%s failed %d", __func__, err);
+        return err;
+}
+
+static int vgpu_gr_gp10b_set_preemption_mode(struct channel_gk20a *ch,
+                                        u32 graphics_preempt_mode,
+                                        u32 compute_preempt_mode)
+{
+        struct gr_ctx_desc *gr_ctx = ch->ch_ctx.gr_ctx;
+        struct gk20a *g = ch->g;
+        struct tsg_gk20a *tsg;
+        struct vm_gk20a *vm;
+        u32 class;
+        int err;
+
+        class = ch->obj_class;
+        if (!class)
+                return -EINVAL;
+
+        /* preemption already set ? */
+        if (gr_ctx->graphics_preempt_mode || gr_ctx->compute_preempt_mode)
+                return -EINVAL;
+
+        if (gk20a_is_channel_marked_as_tsg(ch)) {
+                tsg = &g->fifo.tsg[ch->tsgid];
+                vm = tsg->vm;
+        } else {
+                vm = ch->vm;
+        }
+
+        if (g->ops.gr.set_ctxsw_preemption_mode) {
+                err = g->ops.gr.set_ctxsw_preemption_mode(g, gr_ctx, vm, class,
+                                                graphics_preempt_mode,
+                                                compute_preempt_mode);
+                if (err) {
+                        gk20a_err(dev_from_gk20a(g),
+                                        "set_ctxsw_preemption_mode failed");
+                        return err;
+                }
+        } else {
+                err = -ENOSYS;
+        }
+
+        return err;
+}
+
+static int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g)
+{
+        int err;
+
+        gk20a_dbg_fn("");
+
+        err = vgpu_gr_init_ctx_state(g);
+        if (err)
+                return err;
+
+        vgpu_get_attribute(vgpu_get_handle(g),
+                        TEGRA_VGPU_ATTRIB_PREEMPT_CTX_SIZE,
+                        &g->gr.t18x.ctx_vars.preempt_image_size);
+        if (!g->gr.t18x.ctx_vars.preempt_image_size)
+                return -ENXIO;
+
+        return 0;
+}
+
+void vgpu_gp10b_init_gr_ops(struct gpu_ops *gops)
+{
+        vgpu_gm20b_init_gr_ops(gops);
+        gops->gr.alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx;
+        gops->gr.free_gr_ctx = vgpu_gr_gp10b_free_gr_ctx;
+        gops->gr.init_ctx_state = vgpu_gr_gp10b_init_ctx_state;
+        gops->gr.set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode;
+        gops->gr.set_ctxsw_preemption_mode =
+                        vgpu_gr_gp10b_set_ctxsw_preemption_mode;
+}
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h
new file mode 100644
index 00000000..b3be49a7
--- /dev/null
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef __VGPU_GR_GP10B_H__
+#define __VGPU_GR_GP10B_H__
+
+#include "gk20a/gk20a.h"
+
+void vgpu_gp10b_init_gr_ops(struct gpu_ops *gops);
+
+#endif
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
new file mode 100644
index 00000000..b665a8dd
--- /dev/null
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "vgpu/vgpu.h"
+#include "gp10b/hal_gp10b.h"
+#include "vgpu_gr_gp10b.h"
+#include "vgpu_fifo_gp10b.h"
+#include "vgpu_mm_gp10b.h"
+#include "nvgpu_gpuid_t18x.h"
+
+int vgpu_gp10b_init_hal(struct gk20a *g)
+{
+        int err;
+
+        gk20a_dbg_fn("");
+
+        err = gp10b_init_hal(g);
+        if (err)
+                return err;
+
+        vgpu_init_hal_common(g);
+        vgpu_gp10b_init_gr_ops(&g->ops);
+        vgpu_gp10b_init_fifo_ops(&g->ops);
+        vgpu_gp10b_init_mm_ops(&g->ops);
+        return 0;
+}
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c
new file mode 100644
index 00000000..66fda2d9
--- /dev/null
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c
@@ -0,0 +1,188 @@
+/*
+ * Virtualized GPU Memory Management
+ *
+ * Copyright (c) 2015-2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/dma-mapping.h>
+#include "vgpu/vgpu.h"
+#include "vgpu_mm_gp10b.h"
+#include "gk20a/semaphore_gk20a.h"
+#include "gk20a/mm_gk20a.h"
+
+static int vgpu_gp10b_init_mm_setup_hw(struct gk20a *g)
+{
+        g->mm.bypass_smmu = true;
+        g->mm.disable_bigpage = true;
+        return 0;
+}
+
+static inline int add_mem_desc(struct tegra_vgpu_mem_desc *mem_desc,
+                                u64 addr, u64 size, size_t *oob_size)
+{
+        if (*oob_size < sizeof(*mem_desc))
+                return -ENOMEM;
+
+        mem_desc->addr = addr;
+        mem_desc->length = size;
+        *oob_size -= sizeof(*mem_desc);
+        return 0;
+}
+
+static u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm,
+                                u64 map_offset,
+                                struct sg_table *sgt,
+                                u64 buffer_offset,
+                                u64 size,
+                                int pgsz_idx,
+                                u8 kind_v,
+                                u32 ctag_offset,
+                                u32 flags,
+                                int rw_flag,
+                                bool clear_ctags,
+                                bool sparse,
+                                bool priv,
+                                struct vm_gk20a_mapping_batch *batch,
+                                enum gk20a_aperture aperture)
+{
+        int err = 0;
+        struct device *d = dev_from_vm(vm);
+        struct gk20a *g = gk20a_from_vm(vm);
+        struct tegra_vgpu_cmd_msg msg;
+        struct tegra_vgpu_as_map_ex_params *p = &msg.params.as_map_ex;
+        struct tegra_vgpu_mem_desc *mem_desc;
+        u32 page_size  = vm->gmmu_page_sizes[pgsz_idx];
+        u64 space_to_skip = buffer_offset;
+        u64 buffer_size = 0;
+        u32 mem_desc_count = 0;
+        struct scatterlist *sgl;
+        void *handle = NULL;
+        size_t oob_size;
+        u8 prot;
+
+        gk20a_dbg_fn("");
+
+        /* FIXME: add support for sparse mappings */
+
+        if (WARN_ON(!sgt) || WARN_ON(!g->mm.bypass_smmu))
+                return 0;
+
+        if (space_to_skip & (page_size - 1))
+                return 0;
+
+        /* Allocate (or validate when map_offset != 0) the virtual address. */
+        if (!map_offset) {
+                map_offset = gk20a_vm_alloc_va(vm, size, pgsz_idx);
+                if (!map_offset) {
+                        gk20a_err(d, "failed to allocate va space");
+                        err = -ENOMEM;
+                        goto fail;
+                }
+        }
+
+        handle = tegra_gr_comm_oob_get_ptr(TEGRA_GR_COMM_CTX_CLIENT,
+                                        tegra_gr_comm_get_server_vmid(),
+                                        TEGRA_VGPU_QUEUE_CMD,
+                                        (void **)&mem_desc, &oob_size);
+        if (!handle) {
+                err = -EINVAL;
+                goto fail;
+        }
+
+        sgl = sgt->sgl;
+        while (space_to_skip && sgl &&
+                (space_to_skip + page_size > sgl->length)) {
+                space_to_skip -= sgl->length;
+                sgl = sg_next(sgl);
+        }
+        WARN_ON(!sgl);
+
+        if (add_mem_desc(&mem_desc[mem_desc_count++],
+                        sg_phys(sgl) + space_to_skip,
+                        sgl->length - space_to_skip,
+                        &oob_size)) {
+                err = -ENOMEM;
+                goto fail;
+        }
+        buffer_size += sgl->length - space_to_skip;
+
+        sgl = sg_next(sgl);
+        while (sgl && buffer_size < size) {
+                if (add_mem_desc(&mem_desc[mem_desc_count++], sg_phys(sgl),
+                                sgl->length, &oob_size)) {
+                        err = -ENOMEM;
+                        goto fail;
+                }
+
+                buffer_size += sgl->length;
+                sgl = sg_next(sgl);
+        }
+
+        if (rw_flag == gk20a_mem_flag_read_only)
+                prot = TEGRA_VGPU_MAP_PROT_READ_ONLY;
+        else if (rw_flag == gk20a_mem_flag_write_only)
+                prot = TEGRA_VGPU_MAP_PROT_WRITE_ONLY;
+        else
+                prot = TEGRA_VGPU_MAP_PROT_NONE;
+
+        if (pgsz_idx == gmmu_page_size_kernel) {
+                if (page_size == vm->gmmu_page_sizes[gmmu_page_size_small]) {
+                        pgsz_idx = gmmu_page_size_small;
+                } else if (page_size ==
+                                vm->gmmu_page_sizes[gmmu_page_size_big]) {
+                        pgsz_idx = gmmu_page_size_big;
+                } else {
+                        gk20a_err(d, "invalid kernel page size %d\n",
+                                page_size);
+                        goto fail;
+                }
+        }
+
+        msg.cmd = TEGRA_VGPU_CMD_AS_MAP_EX;
+        msg.handle = vgpu_get_handle(g);
+        p->handle = vm->handle;
+        p->gpu_va = map_offset;
+        p->size = size;
+        p->mem_desc_count = mem_desc_count;
+        p->pgsz_idx = pgsz_idx;
+        p->iova = 0;
+        p->kind = kind_v;
+        p->cacheable =
+                (flags & NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE) ? 1 : 0;
+        p->prot = prot;
+        p->ctag_offset = ctag_offset;
+        p->clear_ctags = clear_ctags;
+        err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
+        if (err || msg.ret)
+                goto fail;
+
+        /* TLB invalidate handled on server side */
+
+        tegra_gr_comm_oob_put_ptr(handle);
+        return map_offset;
+fail:
+        if (handle)
+                tegra_gr_comm_oob_put_ptr(handle);
+        gk20a_err(d, "%s: failed with err=%d\n", __func__, err);
+        return 0;
+}
+
+void vgpu_gp10b_init_mm_ops(struct gpu_ops *gops)
+{
+        gk20a_dbg_fn("");
+
+        gops->mm.gmmu_map = vgpu_gp10b_locked_gmmu_map;
+        gops->mm.init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw;
+
+        /* FIXME: add support for sparse mappings */
+        gops->mm.support_sparse = NULL;
+}
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h
new file mode 100644
index 00000000..5bdc9d1b
--- /dev/null
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef __VGPU_MM_GP10B_H__
+#define __VGPU_MM_GP10B_H__
+
+#include "gk20a/gk20a.h"
+
+void vgpu_gp10b_init_mm_ops(struct gpu_ops *gops);
+
+#endif