diff options
author | Richard Zhao <rizhao@nvidia.com> | 2018-01-30 02:24:37 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-02-27 17:30:52 -0500 |
commit | 6393eddfa996fba03464f897b85aa5ec79860fed (patch) | |
tree | 557ebe9be93e2b0464118e7d8ec019d9d5dbae5f /drivers/gpu/nvgpu/vgpu/gp10b | |
parent | 7932568b7fe9e16b2b83bc58b2b3686c0d5e52d4 (diff) |
gpu: nvgpu: vgpu: move common files out of linux folder
Most of files have been moved out of linux folder. More code could be
common as halifying going on.
Jira EVLR-2364
Change-Id: Ia9dbdbc82f45ceefe5c788eac7517000cd455d5e
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1649947
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/gp10b')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c | 30 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fuse_gp10b.c | 38 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fuse_gp10b.h | 30 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c | 308 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h | 43 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 613 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c | 206 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h | 45 |
8 files changed, 1313 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c new file mode 100644 index 00000000..ac187227 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c | |||
@@ -0,0 +1,30 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include "vgpu_fifo_gp10b.h" | ||
24 | |||
25 | void vgpu_gp10b_init_fifo_ops(struct gpu_ops *gops) | ||
26 | { | ||
27 | /* syncpoint protection not supported yet */ | ||
28 | gops->fifo.resetup_ramfc = NULL; | ||
29 | gops->fifo.reschedule_runlist = NULL; | ||
30 | } | ||
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fuse_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fuse_gp10b.c new file mode 100644 index 00000000..52b2aee5 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fuse_gp10b.c | |||
@@ -0,0 +1,38 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include <nvgpu/enabled.h> | ||
24 | |||
25 | #include "gk20a/gk20a.h" | ||
26 | |||
27 | int vgpu_gp10b_fuse_check_priv_security(struct gk20a *g) | ||
28 | { | ||
29 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | ||
30 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
31 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
32 | } else { | ||
33 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
34 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | ||
35 | } | ||
36 | |||
37 | return 0; | ||
38 | } | ||
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fuse_gp10b.h b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fuse_gp10b.h new file mode 100644 index 00000000..12334f23 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fuse_gp10b.h | |||
@@ -0,0 +1,30 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef _VGPU_GP10B_FUSE | ||
24 | #define _VGPU_GP10B_FUSE | ||
25 | |||
26 | struct gk20a; | ||
27 | |||
28 | int vgpu_gp10b_fuse_check_priv_security(struct gk20a *g); | ||
29 | |||
30 | #endif | ||
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c new file mode 100644 index 00000000..ab35dc67 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c | |||
@@ -0,0 +1,308 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include <nvgpu/kmem.h> | ||
24 | #include <nvgpu/dma.h> | ||
25 | #include <nvgpu/bug.h> | ||
26 | #include <nvgpu/vgpu/vgpu.h> | ||
27 | |||
28 | #include "vgpu/gm20b/vgpu_gr_gm20b.h" | ||
29 | |||
30 | #include "gp10b/gr_gp10b.h" | ||
31 | #include "vgpu_gr_gp10b.h" | ||
32 | |||
33 | #include <nvgpu/hw/gp10b/hw_gr_gp10b.h> | ||
34 | |||
35 | int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, | ||
36 | struct nvgpu_gr_ctx *gr_ctx, | ||
37 | struct vm_gk20a *vm, | ||
38 | u32 class, | ||
39 | u32 flags) | ||
40 | { | ||
41 | u32 graphics_preempt_mode = 0; | ||
42 | u32 compute_preempt_mode = 0; | ||
43 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
44 | int err; | ||
45 | |||
46 | gk20a_dbg_fn(""); | ||
47 | |||
48 | err = vgpu_gr_alloc_gr_ctx(g, gr_ctx, vm, class, flags); | ||
49 | if (err) | ||
50 | return err; | ||
51 | |||
52 | if (flags & NVGPU_OBJ_CTX_FLAGS_SUPPORT_GFXP) | ||
53 | graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; | ||
54 | if (flags & NVGPU_OBJ_CTX_FLAGS_SUPPORT_CILP) | ||
55 | compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP; | ||
56 | |||
57 | if (priv->constants.force_preempt_mode && !graphics_preempt_mode && | ||
58 | !compute_preempt_mode) { | ||
59 | graphics_preempt_mode = g->ops.gr.is_valid_gfx_class(g, class) ? | ||
60 | NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP : 0; | ||
61 | compute_preempt_mode = | ||
62 | g->ops.gr.is_valid_compute_class(g, class) ? | ||
63 | NVGPU_PREEMPTION_MODE_COMPUTE_CTA : 0; | ||
64 | } | ||
65 | |||
66 | if (graphics_preempt_mode || compute_preempt_mode) { | ||
67 | if (g->ops.gr.set_ctxsw_preemption_mode) { | ||
68 | err = g->ops.gr.set_ctxsw_preemption_mode(g, gr_ctx, vm, | ||
69 | class, graphics_preempt_mode, compute_preempt_mode); | ||
70 | if (err) { | ||
71 | nvgpu_err(g, | ||
72 | "set_ctxsw_preemption_mode failed"); | ||
73 | goto fail; | ||
74 | } | ||
75 | } else { | ||
76 | err = -ENOSYS; | ||
77 | goto fail; | ||
78 | } | ||
79 | } | ||
80 | |||
81 | gk20a_dbg_fn("done"); | ||
82 | return err; | ||
83 | |||
84 | fail: | ||
85 | vgpu_gr_free_gr_ctx(g, vm, gr_ctx); | ||
86 | return err; | ||
87 | } | ||
88 | |||
89 | int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, | ||
90 | struct nvgpu_gr_ctx *gr_ctx, | ||
91 | struct vm_gk20a *vm, u32 class, | ||
92 | u32 graphics_preempt_mode, | ||
93 | u32 compute_preempt_mode) | ||
94 | { | ||
95 | struct tegra_vgpu_cmd_msg msg = {}; | ||
96 | struct tegra_vgpu_gr_bind_ctxsw_buffers_params *p = | ||
97 | &msg.params.gr_bind_ctxsw_buffers; | ||
98 | int err = 0; | ||
99 | |||
100 | if (g->ops.gr.is_valid_gfx_class(g, class) && | ||
101 | g->gr.ctx_vars.force_preemption_gfxp) | ||
102 | graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; | ||
103 | |||
104 | if (g->ops.gr.is_valid_compute_class(g, class) && | ||
105 | g->gr.ctx_vars.force_preemption_cilp) | ||
106 | compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP; | ||
107 | |||
108 | /* check for invalid combinations */ | ||
109 | if ((graphics_preempt_mode == 0) && (compute_preempt_mode == 0)) | ||
110 | return -EINVAL; | ||
111 | |||
112 | if ((graphics_preempt_mode == NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP) && | ||
113 | (compute_preempt_mode == NVGPU_PREEMPTION_MODE_COMPUTE_CILP)) | ||
114 | return -EINVAL; | ||
115 | |||
116 | /* set preemption modes */ | ||
117 | switch (graphics_preempt_mode) { | ||
118 | case NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP: | ||
119 | { | ||
120 | u32 spill_size = | ||
121 | gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() * | ||
122 | gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(); | ||
123 | u32 pagepool_size = g->ops.gr.pagepool_default_size(g) * | ||
124 | gr_scc_pagepool_total_pages_byte_granularity_v(); | ||
125 | u32 betacb_size = g->gr.attrib_cb_default_size + | ||
126 | (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - | ||
127 | gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); | ||
128 | u32 attrib_cb_size = (betacb_size + g->gr.alpha_cb_size) * | ||
129 | gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() * | ||
130 | g->gr.max_tpc_count; | ||
131 | struct nvgpu_mem *desc; | ||
132 | |||
133 | attrib_cb_size = ALIGN(attrib_cb_size, 128); | ||
134 | |||
135 | gk20a_dbg_info("gfxp context preempt size=%d", | ||
136 | g->gr.ctx_vars.preempt_image_size); | ||
137 | gk20a_dbg_info("gfxp context spill size=%d", spill_size); | ||
138 | gk20a_dbg_info("gfxp context pagepool size=%d", pagepool_size); | ||
139 | gk20a_dbg_info("gfxp context attrib cb size=%d", | ||
140 | attrib_cb_size); | ||
141 | |||
142 | err = gr_gp10b_alloc_buffer(vm, | ||
143 | g->gr.ctx_vars.preempt_image_size, | ||
144 | &gr_ctx->preempt_ctxsw_buffer); | ||
145 | if (err) { | ||
146 | err = -ENOMEM; | ||
147 | goto fail; | ||
148 | } | ||
149 | desc = &gr_ctx->preempt_ctxsw_buffer; | ||
150 | p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->gpu_va; | ||
151 | p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->size; | ||
152 | |||
153 | err = gr_gp10b_alloc_buffer(vm, | ||
154 | spill_size, | ||
155 | &gr_ctx->spill_ctxsw_buffer); | ||
156 | if (err) { | ||
157 | err = -ENOMEM; | ||
158 | goto fail; | ||
159 | } | ||
160 | desc = &gr_ctx->spill_ctxsw_buffer; | ||
161 | p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->gpu_va; | ||
162 | p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->size; | ||
163 | |||
164 | err = gr_gp10b_alloc_buffer(vm, | ||
165 | pagepool_size, | ||
166 | &gr_ctx->pagepool_ctxsw_buffer); | ||
167 | if (err) { | ||
168 | err = -ENOMEM; | ||
169 | goto fail; | ||
170 | } | ||
171 | desc = &gr_ctx->pagepool_ctxsw_buffer; | ||
172 | p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = | ||
173 | desc->gpu_va; | ||
174 | p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = desc->size; | ||
175 | |||
176 | err = gr_gp10b_alloc_buffer(vm, | ||
177 | attrib_cb_size, | ||
178 | &gr_ctx->betacb_ctxsw_buffer); | ||
179 | if (err) { | ||
180 | err = -ENOMEM; | ||
181 | goto fail; | ||
182 | } | ||
183 | desc = &gr_ctx->betacb_ctxsw_buffer; | ||
184 | p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = | ||
185 | desc->gpu_va; | ||
186 | p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = desc->size; | ||
187 | |||
188 | gr_ctx->graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; | ||
189 | p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_GFX_GFXP; | ||
190 | break; | ||
191 | } | ||
192 | case NVGPU_PREEMPTION_MODE_GRAPHICS_WFI: | ||
193 | gr_ctx->graphics_preempt_mode = graphics_preempt_mode; | ||
194 | break; | ||
195 | |||
196 | default: | ||
197 | break; | ||
198 | } | ||
199 | |||
200 | if (g->ops.gr.is_valid_compute_class(g, class)) { | ||
201 | switch (compute_preempt_mode) { | ||
202 | case NVGPU_PREEMPTION_MODE_COMPUTE_WFI: | ||
203 | gr_ctx->compute_preempt_mode = | ||
204 | NVGPU_PREEMPTION_MODE_COMPUTE_WFI; | ||
205 | p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_WFI; | ||
206 | break; | ||
207 | case NVGPU_PREEMPTION_MODE_COMPUTE_CTA: | ||
208 | gr_ctx->compute_preempt_mode = | ||
209 | NVGPU_PREEMPTION_MODE_COMPUTE_CTA; | ||
210 | p->mode = | ||
211 | TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CTA; | ||
212 | break; | ||
213 | case NVGPU_PREEMPTION_MODE_COMPUTE_CILP: | ||
214 | gr_ctx->compute_preempt_mode = | ||
215 | NVGPU_PREEMPTION_MODE_COMPUTE_CILP; | ||
216 | p->mode = | ||
217 | TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CILP; | ||
218 | break; | ||
219 | default: | ||
220 | break; | ||
221 | } | ||
222 | } | ||
223 | |||
224 | if (gr_ctx->graphics_preempt_mode || gr_ctx->compute_preempt_mode) { | ||
225 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS; | ||
226 | msg.handle = vgpu_get_handle(g); | ||
227 | p->gr_ctx_handle = gr_ctx->virt_ctx; | ||
228 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
229 | if (err || msg.ret) { | ||
230 | err = -ENOMEM; | ||
231 | goto fail; | ||
232 | } | ||
233 | } | ||
234 | |||
235 | return err; | ||
236 | |||
237 | fail: | ||
238 | nvgpu_err(g, "%s failed %d", __func__, err); | ||
239 | return err; | ||
240 | } | ||
241 | |||
242 | int vgpu_gr_gp10b_set_preemption_mode(struct channel_gk20a *ch, | ||
243 | u32 graphics_preempt_mode, | ||
244 | u32 compute_preempt_mode) | ||
245 | { | ||
246 | struct nvgpu_gr_ctx *gr_ctx; | ||
247 | struct gk20a *g = ch->g; | ||
248 | struct tsg_gk20a *tsg; | ||
249 | struct vm_gk20a *vm; | ||
250 | u32 class; | ||
251 | int err; | ||
252 | |||
253 | class = ch->obj_class; | ||
254 | if (!class) | ||
255 | return -EINVAL; | ||
256 | |||
257 | tsg = tsg_gk20a_from_ch(ch); | ||
258 | if (!tsg) | ||
259 | return -EINVAL; | ||
260 | |||
261 | vm = tsg->vm; | ||
262 | gr_ctx = &tsg->gr_ctx; | ||
263 | |||
264 | /* skip setting anything if both modes are already set */ | ||
265 | if (graphics_preempt_mode && | ||
266 | (graphics_preempt_mode == gr_ctx->graphics_preempt_mode)) | ||
267 | graphics_preempt_mode = 0; | ||
268 | |||
269 | if (compute_preempt_mode && | ||
270 | (compute_preempt_mode == gr_ctx->compute_preempt_mode)) | ||
271 | compute_preempt_mode = 0; | ||
272 | |||
273 | if (graphics_preempt_mode == 0 && compute_preempt_mode == 0) | ||
274 | return 0; | ||
275 | |||
276 | if (g->ops.gr.set_ctxsw_preemption_mode) { | ||
277 | err = g->ops.gr.set_ctxsw_preemption_mode(g, gr_ctx, vm, class, | ||
278 | graphics_preempt_mode, | ||
279 | compute_preempt_mode); | ||
280 | if (err) { | ||
281 | nvgpu_err(g, "set_ctxsw_preemption_mode failed"); | ||
282 | return err; | ||
283 | } | ||
284 | } else { | ||
285 | err = -ENOSYS; | ||
286 | } | ||
287 | |||
288 | return err; | ||
289 | } | ||
290 | |||
291 | int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g) | ||
292 | { | ||
293 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
294 | int err; | ||
295 | |||
296 | gk20a_dbg_fn(""); | ||
297 | |||
298 | err = vgpu_gr_init_ctx_state(g); | ||
299 | if (err) | ||
300 | return err; | ||
301 | |||
302 | g->gr.ctx_vars.preempt_image_size = | ||
303 | priv->constants.preempt_ctx_size; | ||
304 | if (!g->gr.ctx_vars.preempt_image_size) | ||
305 | return -EINVAL; | ||
306 | |||
307 | return 0; | ||
308 | } | ||
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h new file mode 100644 index 00000000..0dc53982 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h | |||
@@ -0,0 +1,43 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef __VGPU_GR_GP10B_H__ | ||
24 | #define __VGPU_GR_GP10B_H__ | ||
25 | |||
26 | #include "gk20a/gk20a.h" | ||
27 | |||
28 | int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, | ||
29 | struct nvgpu_gr_ctx *gr_ctx, | ||
30 | struct vm_gk20a *vm, | ||
31 | u32 class, | ||
32 | u32 flags); | ||
33 | int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, | ||
34 | struct nvgpu_gr_ctx *gr_ctx, | ||
35 | struct vm_gk20a *vm, u32 class, | ||
36 | u32 graphics_preempt_mode, | ||
37 | u32 compute_preempt_mode); | ||
38 | int vgpu_gr_gp10b_set_preemption_mode(struct channel_gk20a *ch, | ||
39 | u32 graphics_preempt_mode, | ||
40 | u32 compute_preempt_mode); | ||
41 | int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g); | ||
42 | |||
43 | #endif | ||
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c new file mode 100644 index 00000000..f1ced1c8 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -0,0 +1,613 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include "vgpu/fifo_vgpu.h" | ||
24 | #include "vgpu/gr_vgpu.h" | ||
25 | #include "vgpu/ltc_vgpu.h" | ||
26 | #include "vgpu/mm_vgpu.h" | ||
27 | #include "vgpu/dbg_vgpu.h" | ||
28 | #include "vgpu/fecs_trace_vgpu.h" | ||
29 | #include "vgpu/css_vgpu.h" | ||
30 | #include "gp10b/gp10b.h" | ||
31 | #include "gp10b/hal_gp10b.h" | ||
32 | #include "vgpu/gm20b/vgpu_gr_gm20b.h" | ||
33 | #include "vgpu_gr_gp10b.h" | ||
34 | #include "vgpu_mm_gp10b.h" | ||
35 | #include "vgpu_fuse_gp10b.h" | ||
36 | |||
37 | #include "gk20a/bus_gk20a.h" | ||
38 | #include "gk20a/pramin_gk20a.h" | ||
39 | #include "gk20a/flcn_gk20a.h" | ||
40 | #include "gk20a/mc_gk20a.h" | ||
41 | #include "gk20a/fb_gk20a.h" | ||
42 | |||
43 | #include "gp10b/mc_gp10b.h" | ||
44 | #include "gp10b/ltc_gp10b.h" | ||
45 | #include "gp10b/mm_gp10b.h" | ||
46 | #include "gp10b/ce_gp10b.h" | ||
47 | #include "gp10b/fb_gp10b.h" | ||
48 | #include "gp10b/pmu_gp10b.h" | ||
49 | #include "gp10b/gr_gp10b.h" | ||
50 | #include "gp10b/gr_ctx_gp10b.h" | ||
51 | #include "gp10b/fifo_gp10b.h" | ||
52 | #include "gp10b/gp10b_gating_reglist.h" | ||
53 | #include "gp10b/regops_gp10b.h" | ||
54 | #include "gp10b/therm_gp10b.h" | ||
55 | #include "gp10b/priv_ring_gp10b.h" | ||
56 | |||
57 | #include "gm20b/ltc_gm20b.h" | ||
58 | #include "gm20b/gr_gm20b.h" | ||
59 | #include "gm20b/fifo_gm20b.h" | ||
60 | #include "gm20b/acr_gm20b.h" | ||
61 | #include "gm20b/pmu_gm20b.h" | ||
62 | #include "gm20b/fb_gm20b.h" | ||
63 | #include "gm20b/mm_gm20b.h" | ||
64 | |||
65 | #include <nvgpu/enabled.h> | ||
66 | #include <nvgpu/vgpu/vgpu.h> | ||
67 | |||
68 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> | ||
69 | #include <nvgpu/hw/gp10b/hw_fifo_gp10b.h> | ||
70 | #include <nvgpu/hw/gp10b/hw_ram_gp10b.h> | ||
71 | #include <nvgpu/hw/gp10b/hw_top_gp10b.h> | ||
72 | #include <nvgpu/hw/gp10b/hw_pram_gp10b.h> | ||
73 | #include <nvgpu/hw/gp10b/hw_pwr_gp10b.h> | ||
74 | |||
75 | static const struct gpu_ops vgpu_gp10b_ops = { | ||
76 | .ltc = { | ||
77 | .determine_L2_size_bytes = vgpu_determine_L2_size_bytes, | ||
78 | .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, | ||
79 | .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, | ||
80 | .init_cbc = gm20b_ltc_init_cbc, | ||
81 | .init_fs_state = vgpu_ltc_init_fs_state, | ||
82 | .init_comptags = vgpu_ltc_init_comptags, | ||
83 | .cbc_ctrl = NULL, | ||
84 | .isr = gp10b_ltc_isr, | ||
85 | .cbc_fix_config = gm20b_ltc_cbc_fix_config, | ||
86 | .flush = gm20b_flush_ltc, | ||
87 | .set_enabled = gp10b_ltc_set_enabled, | ||
88 | }, | ||
89 | .ce2 = { | ||
90 | .isr_stall = gp10b_ce_isr, | ||
91 | .isr_nonstall = gp10b_ce_nonstall_isr, | ||
92 | .get_num_pce = vgpu_ce_get_num_pce, | ||
93 | }, | ||
94 | .gr = { | ||
95 | .get_patch_slots = gr_gk20a_get_patch_slots, | ||
96 | .init_gpc_mmu = gr_gm20b_init_gpc_mmu, | ||
97 | .bundle_cb_defaults = gr_gm20b_bundle_cb_defaults, | ||
98 | .cb_size_default = gr_gp10b_cb_size_default, | ||
99 | .calc_global_ctx_buffer_size = | ||
100 | gr_gp10b_calc_global_ctx_buffer_size, | ||
101 | .commit_global_attrib_cb = gr_gp10b_commit_global_attrib_cb, | ||
102 | .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb, | ||
103 | .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager, | ||
104 | .commit_global_pagepool = gr_gp10b_commit_global_pagepool, | ||
105 | .handle_sw_method = gr_gp10b_handle_sw_method, | ||
106 | .set_alpha_circular_buffer_size = | ||
107 | gr_gp10b_set_alpha_circular_buffer_size, | ||
108 | .set_circular_buffer_size = gr_gp10b_set_circular_buffer_size, | ||
109 | .enable_hww_exceptions = gr_gk20a_enable_hww_exceptions, | ||
110 | .is_valid_class = gr_gp10b_is_valid_class, | ||
111 | .is_valid_gfx_class = gr_gp10b_is_valid_gfx_class, | ||
112 | .is_valid_compute_class = gr_gp10b_is_valid_compute_class, | ||
113 | .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs, | ||
114 | .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs, | ||
115 | .init_fs_state = vgpu_gr_init_fs_state, | ||
116 | .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask, | ||
117 | .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, | ||
118 | .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, | ||
119 | .set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask, | ||
120 | .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask, | ||
121 | .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx, | ||
122 | .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull, | ||
123 | .get_zcull_info = vgpu_gr_get_zcull_info, | ||
124 | .is_tpc_addr = gr_gm20b_is_tpc_addr, | ||
125 | .get_tpc_num = gr_gm20b_get_tpc_num, | ||
126 | .detect_sm_arch = vgpu_gr_detect_sm_arch, | ||
127 | .add_zbc_color = gr_gp10b_add_zbc_color, | ||
128 | .add_zbc_depth = gr_gp10b_add_zbc_depth, | ||
129 | .zbc_set_table = vgpu_gr_add_zbc, | ||
130 | .zbc_query_table = vgpu_gr_query_zbc, | ||
131 | .pmu_save_zbc = gk20a_pmu_save_zbc, | ||
132 | .add_zbc = gr_gk20a_add_zbc, | ||
133 | .pagepool_default_size = gr_gp10b_pagepool_default_size, | ||
134 | .init_ctx_state = vgpu_gr_gp10b_init_ctx_state, | ||
135 | .alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx, | ||
136 | .free_gr_ctx = vgpu_gr_free_gr_ctx, | ||
137 | .update_ctxsw_preemption_mode = | ||
138 | gr_gp10b_update_ctxsw_preemption_mode, | ||
139 | .dump_gr_regs = NULL, | ||
140 | .update_pc_sampling = gr_gm20b_update_pc_sampling, | ||
141 | .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask, | ||
142 | .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp, | ||
143 | .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc, | ||
144 | .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask, | ||
145 | .get_max_fbps_count = vgpu_gr_get_max_fbps_count, | ||
146 | .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info, | ||
147 | .wait_empty = gr_gp10b_wait_empty, | ||
148 | .init_cyclestats = vgpu_gr_gm20b_init_cyclestats, | ||
149 | .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode, | ||
150 | .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, | ||
151 | .bpt_reg_info = gr_gm20b_bpt_reg_info, | ||
152 | .get_access_map = gr_gp10b_get_access_map, | ||
153 | .handle_fecs_error = gr_gp10b_handle_fecs_error, | ||
154 | .handle_sm_exception = gr_gp10b_handle_sm_exception, | ||
155 | .handle_tex_exception = gr_gp10b_handle_tex_exception, | ||
156 | .enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions, | ||
157 | .enable_exceptions = gk20a_gr_enable_exceptions, | ||
158 | .get_lrf_tex_ltc_dram_override = get_ecc_override_val, | ||
159 | .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode, | ||
160 | .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode, | ||
161 | .record_sm_error_state = gm20b_gr_record_sm_error_state, | ||
162 | .update_sm_error_state = gm20b_gr_update_sm_error_state, | ||
163 | .clear_sm_error_state = vgpu_gr_clear_sm_error_state, | ||
164 | .suspend_contexts = vgpu_gr_suspend_contexts, | ||
165 | .resume_contexts = vgpu_gr_resume_contexts, | ||
166 | .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, | ||
167 | .init_sm_id_table = vgpu_gr_init_sm_id_table, | ||
168 | .load_smid_config = gr_gp10b_load_smid_config, | ||
169 | .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering, | ||
170 | .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, | ||
171 | .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr, | ||
172 | .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr, | ||
173 | .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr, | ||
174 | .setup_rop_mapping = gr_gk20a_setup_rop_mapping, | ||
175 | .program_zcull_mapping = gr_gk20a_program_zcull_mapping, | ||
176 | .commit_global_timeslice = gr_gk20a_commit_global_timeslice, | ||
177 | .commit_inst = vgpu_gr_commit_inst, | ||
178 | .write_zcull_ptr = gr_gk20a_write_zcull_ptr, | ||
179 | .write_pm_ptr = gr_gk20a_write_pm_ptr, | ||
180 | .init_elcg_mode = gr_gk20a_init_elcg_mode, | ||
181 | .load_tpc_mask = gr_gm20b_load_tpc_mask, | ||
182 | .inval_icache = gr_gk20a_inval_icache, | ||
183 | .trigger_suspend = gr_gk20a_trigger_suspend, | ||
184 | .wait_for_pause = gr_gk20a_wait_for_pause, | ||
185 | .resume_from_pause = gr_gk20a_resume_from_pause, | ||
186 | .clear_sm_errors = gr_gk20a_clear_sm_errors, | ||
187 | .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions, | ||
188 | .get_esr_sm_sel = gk20a_gr_get_esr_sm_sel, | ||
189 | .sm_debugger_attached = gk20a_gr_sm_debugger_attached, | ||
190 | .suspend_single_sm = gk20a_gr_suspend_single_sm, | ||
191 | .suspend_all_sms = gk20a_gr_suspend_all_sms, | ||
192 | .resume_single_sm = gk20a_gr_resume_single_sm, | ||
193 | .resume_all_sms = gk20a_gr_resume_all_sms, | ||
194 | .get_sm_hww_warp_esr = gp10b_gr_get_sm_hww_warp_esr, | ||
195 | .get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr, | ||
196 | .get_sm_no_lock_down_hww_global_esr_mask = | ||
197 | gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask, | ||
198 | .lock_down_sm = gk20a_gr_lock_down_sm, | ||
199 | .wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down, | ||
200 | .clear_sm_hww = gm20b_gr_clear_sm_hww, | ||
201 | .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf, | ||
202 | .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs, | ||
203 | .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, | ||
204 | .set_boosted_ctx = NULL, | ||
205 | .set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode, | ||
206 | .set_czf_bypass = gr_gp10b_set_czf_bypass, | ||
207 | .init_czf_bypass = gr_gp10b_init_czf_bypass, | ||
208 | .pre_process_sm_exception = gr_gp10b_pre_process_sm_exception, | ||
209 | .set_preemption_buffer_va = gr_gp10b_set_preemption_buffer_va, | ||
210 | .init_preemption_state = gr_gp10b_init_preemption_state, | ||
211 | .update_boosted_ctx = NULL, | ||
212 | .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, | ||
213 | .set_bes_crop_debug4 = gr_gp10b_set_bes_crop_debug4, | ||
214 | .create_gr_sysfs = gr_gp10b_create_sysfs, | ||
215 | .set_ctxsw_preemption_mode = | ||
216 | vgpu_gr_gp10b_set_ctxsw_preemption_mode, | ||
217 | .init_ctxsw_hdr_data = gr_gp10b_init_ctxsw_hdr_data, | ||
218 | .init_gfxp_wfi_timeout_count = | ||
219 | gr_gp10b_init_gfxp_wfi_timeout_count, | ||
220 | .get_max_gfxp_wfi_timeout_count = | ||
221 | gr_gp10b_get_max_gfxp_wfi_timeout_count, | ||
222 | }, | ||
223 | .fb = { | ||
224 | .reset = fb_gk20a_reset, | ||
225 | .init_hw = gk20a_fb_init_hw, | ||
226 | .init_fs_state = fb_gm20b_init_fs_state, | ||
227 | .set_mmu_page_size = gm20b_fb_set_mmu_page_size, | ||
228 | .set_use_full_comp_tag_line = | ||
229 | gm20b_fb_set_use_full_comp_tag_line, | ||
230 | .compression_page_size = gp10b_fb_compression_page_size, | ||
231 | .compressible_page_size = gp10b_fb_compressible_page_size, | ||
232 | .compression_align_mask = gm20b_fb_compression_align_mask, | ||
233 | .vpr_info_fetch = gm20b_fb_vpr_info_fetch, | ||
234 | .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, | ||
235 | .read_wpr_info = gm20b_fb_read_wpr_info, | ||
236 | .is_debug_mode_enabled = NULL, | ||
237 | .set_debug_mode = vgpu_mm_mmu_set_debug_mode, | ||
238 | .tlb_invalidate = vgpu_mm_tlb_invalidate, | ||
239 | }, | ||
240 | .clock_gating = { | ||
241 | .slcg_bus_load_gating_prod = | ||
242 | gp10b_slcg_bus_load_gating_prod, | ||
243 | .slcg_ce2_load_gating_prod = | ||
244 | gp10b_slcg_ce2_load_gating_prod, | ||
245 | .slcg_chiplet_load_gating_prod = | ||
246 | gp10b_slcg_chiplet_load_gating_prod, | ||
247 | .slcg_ctxsw_firmware_load_gating_prod = | ||
248 | gp10b_slcg_ctxsw_firmware_load_gating_prod, | ||
249 | .slcg_fb_load_gating_prod = | ||
250 | gp10b_slcg_fb_load_gating_prod, | ||
251 | .slcg_fifo_load_gating_prod = | ||
252 | gp10b_slcg_fifo_load_gating_prod, | ||
253 | .slcg_gr_load_gating_prod = | ||
254 | gr_gp10b_slcg_gr_load_gating_prod, | ||
255 | .slcg_ltc_load_gating_prod = | ||
256 | ltc_gp10b_slcg_ltc_load_gating_prod, | ||
257 | .slcg_perf_load_gating_prod = | ||
258 | gp10b_slcg_perf_load_gating_prod, | ||
259 | .slcg_priring_load_gating_prod = | ||
260 | gp10b_slcg_priring_load_gating_prod, | ||
261 | .slcg_pmu_load_gating_prod = | ||
262 | gp10b_slcg_pmu_load_gating_prod, | ||
263 | .slcg_therm_load_gating_prod = | ||
264 | gp10b_slcg_therm_load_gating_prod, | ||
265 | .slcg_xbar_load_gating_prod = | ||
266 | gp10b_slcg_xbar_load_gating_prod, | ||
267 | .blcg_bus_load_gating_prod = | ||
268 | gp10b_blcg_bus_load_gating_prod, | ||
269 | .blcg_ce_load_gating_prod = | ||
270 | gp10b_blcg_ce_load_gating_prod, | ||
271 | .blcg_ctxsw_firmware_load_gating_prod = | ||
272 | gp10b_blcg_ctxsw_firmware_load_gating_prod, | ||
273 | .blcg_fb_load_gating_prod = | ||
274 | gp10b_blcg_fb_load_gating_prod, | ||
275 | .blcg_fifo_load_gating_prod = | ||
276 | gp10b_blcg_fifo_load_gating_prod, | ||
277 | .blcg_gr_load_gating_prod = | ||
278 | gp10b_blcg_gr_load_gating_prod, | ||
279 | .blcg_ltc_load_gating_prod = | ||
280 | gp10b_blcg_ltc_load_gating_prod, | ||
281 | .blcg_pwr_csb_load_gating_prod = | ||
282 | gp10b_blcg_pwr_csb_load_gating_prod, | ||
283 | .blcg_pmu_load_gating_prod = | ||
284 | gp10b_blcg_pmu_load_gating_prod, | ||
285 | .blcg_xbar_load_gating_prod = | ||
286 | gp10b_blcg_xbar_load_gating_prod, | ||
287 | .pg_gr_load_gating_prod = | ||
288 | gr_gp10b_pg_gr_load_gating_prod, | ||
289 | }, | ||
290 | .fifo = { | ||
291 | .init_fifo_setup_hw = vgpu_init_fifo_setup_hw, | ||
292 | .bind_channel = vgpu_channel_bind, | ||
293 | .unbind_channel = vgpu_channel_unbind, | ||
294 | .disable_channel = vgpu_channel_disable, | ||
295 | .enable_channel = vgpu_channel_enable, | ||
296 | .alloc_inst = vgpu_channel_alloc_inst, | ||
297 | .free_inst = vgpu_channel_free_inst, | ||
298 | .setup_ramfc = vgpu_channel_setup_ramfc, | ||
299 | .default_timeslice_us = vgpu_fifo_default_timeslice_us, | ||
300 | .setup_userd = gk20a_fifo_setup_userd, | ||
301 | .userd_gp_get = gk20a_fifo_userd_gp_get, | ||
302 | .userd_gp_put = gk20a_fifo_userd_gp_put, | ||
303 | .userd_pb_get = gk20a_fifo_userd_pb_get, | ||
304 | .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, | ||
305 | .preempt_channel = vgpu_fifo_preempt_channel, | ||
306 | .preempt_tsg = vgpu_fifo_preempt_tsg, | ||
307 | .enable_tsg = vgpu_enable_tsg, | ||
308 | .disable_tsg = gk20a_disable_tsg, | ||
309 | .tsg_verify_channel_status = NULL, | ||
310 | .tsg_verify_status_ctx_reload = NULL, | ||
311 | .reschedule_runlist = NULL, | ||
312 | .update_runlist = vgpu_fifo_update_runlist, | ||
313 | .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault, | ||
314 | .get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info, | ||
315 | .wait_engine_idle = vgpu_fifo_wait_engine_idle, | ||
316 | .get_num_fifos = gm20b_fifo_get_num_fifos, | ||
317 | .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, | ||
318 | .set_runlist_interleave = vgpu_fifo_set_runlist_interleave, | ||
319 | .tsg_set_timeslice = vgpu_tsg_set_timeslice, | ||
320 | .tsg_open = vgpu_tsg_open, | ||
321 | .force_reset_ch = vgpu_fifo_force_reset_ch, | ||
322 | .engine_enum_from_type = gp10b_fifo_engine_enum_from_type, | ||
323 | .device_info_data_parse = gp10b_device_info_data_parse, | ||
324 | .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v, | ||
325 | .init_engine_info = vgpu_fifo_init_engine_info, | ||
326 | .runlist_entry_size = ram_rl_entry_size_v, | ||
327 | .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry, | ||
328 | .get_ch_runlist_entry = gk20a_get_ch_runlist_entry, | ||
329 | .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc, | ||
330 | .dump_pbdma_status = gk20a_dump_pbdma_status, | ||
331 | .dump_eng_status = gk20a_dump_eng_status, | ||
332 | .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc, | ||
333 | .intr_0_error_mask = gk20a_fifo_intr_0_error_mask, | ||
334 | .is_preempt_pending = gk20a_fifo_is_preempt_pending, | ||
335 | .init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs, | ||
336 | .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, | ||
337 | .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg, | ||
338 | .handle_sched_error = gk20a_fifo_handle_sched_error, | ||
339 | .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0, | ||
340 | .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1, | ||
341 | .tsg_bind_channel = vgpu_tsg_bind_channel, | ||
342 | .tsg_unbind_channel = vgpu_tsg_unbind_channel, | ||
343 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | ||
344 | .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf, | ||
345 | .free_syncpt_buf = gk20a_fifo_free_syncpt_buf, | ||
346 | .add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd, | ||
347 | .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size, | ||
348 | .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd, | ||
349 | .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size, | ||
350 | .get_sync_ro_map = NULL, | ||
351 | #endif | ||
352 | .resetup_ramfc = NULL, | ||
353 | .device_info_fault_id = top_device_info_data_fault_id_enum_v, | ||
354 | }, | ||
355 | .gr_ctx = { | ||
356 | .get_netlist_name = gr_gp10b_get_netlist_name, | ||
357 | .is_fw_defined = gr_gp10b_is_firmware_defined, | ||
358 | }, | ||
359 | #ifdef CONFIG_GK20A_CTXSW_TRACE | ||
360 | .fecs_trace = { | ||
361 | .alloc_user_buffer = vgpu_alloc_user_buffer, | ||
362 | .free_user_buffer = vgpu_free_user_buffer, | ||
363 | .mmap_user_buffer = vgpu_mmap_user_buffer, | ||
364 | .init = vgpu_fecs_trace_init, | ||
365 | .deinit = vgpu_fecs_trace_deinit, | ||
366 | .enable = vgpu_fecs_trace_enable, | ||
367 | .disable = vgpu_fecs_trace_disable, | ||
368 | .is_enabled = vgpu_fecs_trace_is_enabled, | ||
369 | .reset = NULL, | ||
370 | .flush = NULL, | ||
371 | .poll = vgpu_fecs_trace_poll, | ||
372 | .bind_channel = NULL, | ||
373 | .unbind_channel = NULL, | ||
374 | .max_entries = vgpu_fecs_trace_max_entries, | ||
375 | .set_filter = vgpu_fecs_trace_set_filter, | ||
376 | }, | ||
377 | #endif /* CONFIG_GK20A_CTXSW_TRACE */ | ||
378 | .mm = { | ||
379 | /* FIXME: add support for sparse mappings */ | ||
380 | .support_sparse = NULL, | ||
381 | .gmmu_map = vgpu_gp10b_locked_gmmu_map, | ||
382 | .gmmu_unmap = vgpu_locked_gmmu_unmap, | ||
383 | .vm_bind_channel = vgpu_vm_bind_channel, | ||
384 | .fb_flush = vgpu_mm_fb_flush, | ||
385 | .l2_invalidate = vgpu_mm_l2_invalidate, | ||
386 | .l2_flush = vgpu_mm_l2_flush, | ||
387 | .cbc_clean = gk20a_mm_cbc_clean, | ||
388 | .set_big_page_size = gm20b_mm_set_big_page_size, | ||
389 | .get_big_page_sizes = gm20b_mm_get_big_page_sizes, | ||
390 | .get_default_big_page_size = gp10b_mm_get_default_big_page_size, | ||
391 | .gpu_phys_addr = gm20b_gpu_phys_addr, | ||
392 | .get_iommu_bit = gk20a_mm_get_iommu_bit, | ||
393 | .get_mmu_levels = gp10b_mm_get_mmu_levels, | ||
394 | .init_pdb = gp10b_mm_init_pdb, | ||
395 | .init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw, | ||
396 | .is_bar1_supported = gm20b_mm_is_bar1_supported, | ||
397 | .init_inst_block = gk20a_init_inst_block, | ||
398 | .mmu_fault_pending = gk20a_fifo_mmu_fault_pending, | ||
399 | .init_bar2_vm = gp10b_init_bar2_vm, | ||
400 | .init_bar2_mm_hw_setup = gp10b_init_bar2_mm_hw_setup, | ||
401 | .remove_bar2_vm = gp10b_remove_bar2_vm, | ||
402 | .get_kind_invalid = gm20b_get_kind_invalid, | ||
403 | .get_kind_pitch = gm20b_get_kind_pitch, | ||
404 | }, | ||
405 | .pramin = { | ||
406 | .enter = gk20a_pramin_enter, | ||
407 | .exit = gk20a_pramin_exit, | ||
408 | .data032_r = pram_data032_r, | ||
409 | }, | ||
410 | .therm = { | ||
411 | .init_therm_setup_hw = gp10b_init_therm_setup_hw, | ||
412 | .elcg_init_idle_filters = gp10b_elcg_init_idle_filters, | ||
413 | }, | ||
414 | .pmu = { | ||
415 | .pmu_setup_elpg = gp10b_pmu_setup_elpg, | ||
416 | .pmu_get_queue_head = pwr_pmu_queue_head_r, | ||
417 | .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, | ||
418 | .pmu_get_queue_tail = pwr_pmu_queue_tail_r, | ||
419 | .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, | ||
420 | .pmu_queue_head = gk20a_pmu_queue_head, | ||
421 | .pmu_queue_tail = gk20a_pmu_queue_tail, | ||
422 | .pmu_msgq_tail = gk20a_pmu_msgq_tail, | ||
423 | .pmu_mutex_size = pwr_pmu_mutex__size_1_v, | ||
424 | .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, | ||
425 | .pmu_mutex_release = gk20a_pmu_mutex_release, | ||
426 | .write_dmatrfbase = gp10b_write_dmatrfbase, | ||
427 | .pmu_elpg_statistics = gp10b_pmu_elpg_statistics, | ||
428 | .pmu_init_perfmon = nvgpu_pmu_init_perfmon, | ||
429 | .pmu_perfmon_start_sampling = nvgpu_pmu_perfmon_start_sampling, | ||
430 | .pmu_perfmon_stop_sampling = nvgpu_pmu_perfmon_stop_sampling, | ||
431 | .pmu_pg_init_param = gp10b_pg_gr_init, | ||
432 | .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, | ||
433 | .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, | ||
434 | .dump_secure_fuses = pmu_dump_security_fuses_gp10b, | ||
435 | .reset_engine = gk20a_pmu_engine_reset, | ||
436 | .is_engine_in_reset = gk20a_pmu_is_engine_in_reset, | ||
437 | }, | ||
438 | .regops = { | ||
439 | .get_global_whitelist_ranges = | ||
440 | gp10b_get_global_whitelist_ranges, | ||
441 | .get_global_whitelist_ranges_count = | ||
442 | gp10b_get_global_whitelist_ranges_count, | ||
443 | .get_context_whitelist_ranges = | ||
444 | gp10b_get_context_whitelist_ranges, | ||
445 | .get_context_whitelist_ranges_count = | ||
446 | gp10b_get_context_whitelist_ranges_count, | ||
447 | .get_runcontrol_whitelist = gp10b_get_runcontrol_whitelist, | ||
448 | .get_runcontrol_whitelist_count = | ||
449 | gp10b_get_runcontrol_whitelist_count, | ||
450 | .get_runcontrol_whitelist_ranges = | ||
451 | gp10b_get_runcontrol_whitelist_ranges, | ||
452 | .get_runcontrol_whitelist_ranges_count = | ||
453 | gp10b_get_runcontrol_whitelist_ranges_count, | ||
454 | .get_qctl_whitelist = gp10b_get_qctl_whitelist, | ||
455 | .get_qctl_whitelist_count = gp10b_get_qctl_whitelist_count, | ||
456 | .get_qctl_whitelist_ranges = gp10b_get_qctl_whitelist_ranges, | ||
457 | .get_qctl_whitelist_ranges_count = | ||
458 | gp10b_get_qctl_whitelist_ranges_count, | ||
459 | .apply_smpc_war = gp10b_apply_smpc_war, | ||
460 | }, | ||
461 | .mc = { | ||
462 | .intr_enable = mc_gp10b_intr_enable, | ||
463 | .intr_unit_config = mc_gp10b_intr_unit_config, | ||
464 | .isr_stall = mc_gp10b_isr_stall, | ||
465 | .intr_stall = mc_gp10b_intr_stall, | ||
466 | .intr_stall_pause = mc_gp10b_intr_stall_pause, | ||
467 | .intr_stall_resume = mc_gp10b_intr_stall_resume, | ||
468 | .intr_nonstall = mc_gp10b_intr_nonstall, | ||
469 | .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, | ||
470 | .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, | ||
471 | .enable = gk20a_mc_enable, | ||
472 | .disable = gk20a_mc_disable, | ||
473 | .reset = gk20a_mc_reset, | ||
474 | .boot_0 = gk20a_mc_boot_0, | ||
475 | .is_intr1_pending = mc_gp10b_is_intr1_pending, | ||
476 | }, | ||
477 | .debug = { | ||
478 | .show_dump = NULL, | ||
479 | }, | ||
480 | .dbg_session_ops = { | ||
481 | .exec_reg_ops = vgpu_exec_regops, | ||
482 | .dbg_set_powergate = vgpu_dbg_set_powergate, | ||
483 | .check_and_set_global_reservation = | ||
484 | vgpu_check_and_set_global_reservation, | ||
485 | .check_and_set_context_reservation = | ||
486 | vgpu_check_and_set_context_reservation, | ||
487 | .release_profiler_reservation = | ||
488 | vgpu_release_profiler_reservation, | ||
489 | .perfbuffer_enable = vgpu_perfbuffer_enable, | ||
490 | .perfbuffer_disable = vgpu_perfbuffer_disable, | ||
491 | }, | ||
492 | .bus = { | ||
493 | .init_hw = gk20a_bus_init_hw, | ||
494 | .isr = gk20a_bus_isr, | ||
495 | .read_ptimer = vgpu_read_ptimer, | ||
496 | .get_timestamps_zipper = vgpu_get_timestamps_zipper, | ||
497 | .bar1_bind = gk20a_bus_bar1_bind, | ||
498 | }, | ||
499 | #if defined(CONFIG_GK20A_CYCLE_STATS) | ||
500 | .css = { | ||
501 | .enable_snapshot = vgpu_css_enable_snapshot_buffer, | ||
502 | .disable_snapshot = vgpu_css_release_snapshot_buffer, | ||
503 | .check_data_available = vgpu_css_flush_snapshots, | ||
504 | .detach_snapshot = vgpu_css_detach, | ||
505 | .set_handled_snapshots = NULL, | ||
506 | .allocate_perfmon_ids = NULL, | ||
507 | .release_perfmon_ids = NULL, | ||
508 | }, | ||
509 | #endif | ||
510 | .falcon = { | ||
511 | .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, | ||
512 | }, | ||
513 | .priv_ring = { | ||
514 | .isr = gp10b_priv_ring_isr, | ||
515 | }, | ||
516 | .fuse = { | ||
517 | .check_priv_security = vgpu_gp10b_fuse_check_priv_security, | ||
518 | }, | ||
519 | .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics, | ||
520 | .get_litter_value = gp10b_get_litter_value, | ||
521 | }; | ||
522 | |||
523 | int vgpu_gp10b_init_hal(struct gk20a *g) | ||
524 | { | ||
525 | struct gpu_ops *gops = &g->ops; | ||
526 | |||
527 | gops->ltc = vgpu_gp10b_ops.ltc; | ||
528 | gops->ce2 = vgpu_gp10b_ops.ce2; | ||
529 | gops->gr = vgpu_gp10b_ops.gr; | ||
530 | gops->fb = vgpu_gp10b_ops.fb; | ||
531 | gops->clock_gating = vgpu_gp10b_ops.clock_gating; | ||
532 | gops->fifo = vgpu_gp10b_ops.fifo; | ||
533 | gops->gr_ctx = vgpu_gp10b_ops.gr_ctx; | ||
534 | #ifdef CONFIG_GK20A_CTXSW_TRACE | ||
535 | gops->fecs_trace = vgpu_gp10b_ops.fecs_trace; | ||
536 | #endif | ||
537 | gops->mm = vgpu_gp10b_ops.mm; | ||
538 | gops->pramin = vgpu_gp10b_ops.pramin; | ||
539 | gops->therm = vgpu_gp10b_ops.therm; | ||
540 | gops->pmu = vgpu_gp10b_ops.pmu; | ||
541 | gops->regops = vgpu_gp10b_ops.regops; | ||
542 | gops->mc = vgpu_gp10b_ops.mc; | ||
543 | gops->debug = vgpu_gp10b_ops.debug; | ||
544 | gops->dbg_session_ops = vgpu_gp10b_ops.dbg_session_ops; | ||
545 | gops->bus = vgpu_gp10b_ops.bus; | ||
546 | #if defined(CONFIG_GK20A_CYCLE_STATS) | ||
547 | gops->css = vgpu_gp10b_ops.css; | ||
548 | #endif | ||
549 | gops->falcon = vgpu_gp10b_ops.falcon; | ||
550 | |||
551 | gops->priv_ring = vgpu_gp10b_ops.priv_ring; | ||
552 | |||
553 | gops->fuse = vgpu_gp10b_ops.fuse; | ||
554 | |||
555 | /* Lone Functions */ | ||
556 | gops->chip_init_gpu_characteristics = | ||
557 | vgpu_gp10b_ops.chip_init_gpu_characteristics; | ||
558 | gops->get_litter_value = vgpu_gp10b_ops.get_litter_value; | ||
559 | |||
560 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | ||
561 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | ||
562 | |||
563 | /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ | ||
564 | if (gops->fuse.check_priv_security(g)) | ||
565 | return -EINVAL; /* Do not boot gpu */ | ||
566 | |||
567 | /* priv security dependent ops */ | ||
568 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { | ||
569 | /* Add in ops from gm20b acr */ | ||
570 | gops->pmu.is_pmu_supported = gm20b_is_pmu_supported, | ||
571 | gops->pmu.prepare_ucode = prepare_ucode_blob, | ||
572 | gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn, | ||
573 | gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap, | ||
574 | gops->pmu.is_priv_load = gm20b_is_priv_load, | ||
575 | gops->pmu.get_wpr = gm20b_wpr_info, | ||
576 | gops->pmu.alloc_blob_space = gm20b_alloc_blob_space, | ||
577 | gops->pmu.pmu_populate_loader_cfg = | ||
578 | gm20b_pmu_populate_loader_cfg, | ||
579 | gops->pmu.flcn_populate_bl_dmem_desc = | ||
580 | gm20b_flcn_populate_bl_dmem_desc, | ||
581 | gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt, | ||
582 | gops->pmu.falcon_clear_halt_interrupt_status = | ||
583 | clear_halt_interrupt_status, | ||
584 | gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1, | ||
585 | |||
586 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; | ||
587 | gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; | ||
588 | gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap; | ||
589 | gops->pmu.is_priv_load = gp10b_is_priv_load; | ||
590 | |||
591 | gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; | ||
592 | } else { | ||
593 | /* Inherit from gk20a */ | ||
594 | gops->pmu.is_pmu_supported = gk20a_is_pmu_supported, | ||
595 | gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob, | ||
596 | gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1, | ||
597 | gops->pmu.pmu_nsbootstrap = pmu_bootstrap, | ||
598 | |||
599 | gops->pmu.load_lsfalcon_ucode = NULL; | ||
600 | gops->pmu.init_wpr_region = NULL; | ||
601 | gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; | ||
602 | |||
603 | gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; | ||
604 | } | ||
605 | |||
606 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); | ||
607 | g->pmu_lsf_pmu_wpr_init_done = 0; | ||
608 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; | ||
609 | |||
610 | g->name = "gp10b"; | ||
611 | |||
612 | return 0; | ||
613 | } | ||
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c new file mode 100644 index 00000000..cf9a28c7 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c | |||
@@ -0,0 +1,206 @@ | |||
1 | /* | ||
2 | * Virtualized GPU Memory Management | ||
3 | * | ||
4 | * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include "vgpu_mm_gp10b.h" | ||
26 | #include "gk20a/mm_gk20a.h" | ||
27 | |||
28 | #include <nvgpu/bug.h> | ||
29 | #include <nvgpu/dma.h> | ||
30 | #include <nvgpu/vgpu/vgpu_ivc.h> | ||
31 | #include <nvgpu/vgpu/vgpu.h> | ||
32 | |||
33 | int vgpu_gp10b_init_mm_setup_hw(struct gk20a *g) | ||
34 | { | ||
35 | g->mm.disable_bigpage = true; | ||
36 | return 0; | ||
37 | } | ||
38 | |||
39 | static inline int add_mem_desc(struct tegra_vgpu_mem_desc *mem_desc, | ||
40 | u64 addr, u64 size, size_t *oob_size) | ||
41 | { | ||
42 | if (*oob_size < sizeof(*mem_desc)) | ||
43 | return -ENOMEM; | ||
44 | |||
45 | mem_desc->addr = addr; | ||
46 | mem_desc->length = size; | ||
47 | *oob_size -= sizeof(*mem_desc); | ||
48 | return 0; | ||
49 | } | ||
50 | |||
51 | u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm, | ||
52 | u64 map_offset, | ||
53 | struct nvgpu_sgt *sgt, | ||
54 | u64 buffer_offset, | ||
55 | u64 size, | ||
56 | int pgsz_idx, | ||
57 | u8 kind_v, | ||
58 | u32 ctag_offset, | ||
59 | u32 flags, | ||
60 | int rw_flag, | ||
61 | bool clear_ctags, | ||
62 | bool sparse, | ||
63 | bool priv, | ||
64 | struct vm_gk20a_mapping_batch *batch, | ||
65 | enum nvgpu_aperture aperture) | ||
66 | { | ||
67 | int err = 0; | ||
68 | struct gk20a *g = gk20a_from_vm(vm); | ||
69 | struct tegra_vgpu_cmd_msg msg; | ||
70 | struct tegra_vgpu_as_map_ex_params *p = &msg.params.as_map_ex; | ||
71 | struct tegra_vgpu_mem_desc *mem_desc; | ||
72 | u32 page_size = vm->gmmu_page_sizes[pgsz_idx]; | ||
73 | u64 buffer_size = PAGE_ALIGN(size); | ||
74 | u64 space_to_skip = buffer_offset; | ||
75 | u32 mem_desc_count = 0, i; | ||
76 | void *handle = NULL; | ||
77 | size_t oob_size; | ||
78 | u8 prot; | ||
79 | void *sgl; | ||
80 | |||
81 | gk20a_dbg_fn(""); | ||
82 | |||
83 | /* FIXME: add support for sparse mappings */ | ||
84 | |||
85 | if (WARN_ON(!sgt) || WARN_ON(nvgpu_iommuable(g))) | ||
86 | return 0; | ||
87 | |||
88 | if (space_to_skip & (page_size - 1)) | ||
89 | return 0; | ||
90 | |||
91 | memset(&msg, 0, sizeof(msg)); | ||
92 | |||
93 | /* Allocate (or validate when map_offset != 0) the virtual address. */ | ||
94 | if (!map_offset) { | ||
95 | map_offset = __nvgpu_vm_alloc_va(vm, size, pgsz_idx); | ||
96 | if (!map_offset) { | ||
97 | nvgpu_err(g, "failed to allocate va space"); | ||
98 | err = -ENOMEM; | ||
99 | goto fail; | ||
100 | } | ||
101 | } | ||
102 | |||
103 | handle = vgpu_ivc_oob_get_ptr(vgpu_ivc_get_server_vmid(), | ||
104 | TEGRA_VGPU_QUEUE_CMD, | ||
105 | (void **)&mem_desc, &oob_size); | ||
106 | if (!handle) { | ||
107 | err = -EINVAL; | ||
108 | goto fail; | ||
109 | } | ||
110 | sgl = sgt->sgl; | ||
111 | while (sgl) { | ||
112 | u64 phys_addr; | ||
113 | u64 chunk_length; | ||
114 | |||
115 | /* | ||
116 | * Cut out sgl ents for space_to_skip. | ||
117 | */ | ||
118 | if (space_to_skip && | ||
119 | space_to_skip >= nvgpu_sgt_get_length(sgt, sgl)) { | ||
120 | space_to_skip -= nvgpu_sgt_get_length(sgt, sgl); | ||
121 | sgl = nvgpu_sgt_get_next(sgt, sgl); | ||
122 | continue; | ||
123 | } | ||
124 | |||
125 | phys_addr = nvgpu_sgt_get_phys(sgt, sgl) + space_to_skip; | ||
126 | chunk_length = min(size, | ||
127 | nvgpu_sgt_get_length(sgt, sgl) - space_to_skip); | ||
128 | |||
129 | if (add_mem_desc(&mem_desc[mem_desc_count++], phys_addr, | ||
130 | chunk_length, &oob_size)) { | ||
131 | err = -ENOMEM; | ||
132 | goto fail; | ||
133 | } | ||
134 | |||
135 | space_to_skip = 0; | ||
136 | size -= chunk_length; | ||
137 | sgl = nvgpu_sgt_get_next(sgt, sgl); | ||
138 | |||
139 | if (size == 0) | ||
140 | break; | ||
141 | } | ||
142 | |||
143 | if (rw_flag == gk20a_mem_flag_read_only) | ||
144 | prot = TEGRA_VGPU_MAP_PROT_READ_ONLY; | ||
145 | else if (rw_flag == gk20a_mem_flag_write_only) | ||
146 | prot = TEGRA_VGPU_MAP_PROT_WRITE_ONLY; | ||
147 | else | ||
148 | prot = TEGRA_VGPU_MAP_PROT_NONE; | ||
149 | |||
150 | if (pgsz_idx == gmmu_page_size_kernel) { | ||
151 | if (page_size == vm->gmmu_page_sizes[gmmu_page_size_small]) { | ||
152 | pgsz_idx = gmmu_page_size_small; | ||
153 | } else if (page_size == | ||
154 | vm->gmmu_page_sizes[gmmu_page_size_big]) { | ||
155 | pgsz_idx = gmmu_page_size_big; | ||
156 | } else { | ||
157 | nvgpu_err(g, "invalid kernel page size %d", | ||
158 | page_size); | ||
159 | goto fail; | ||
160 | } | ||
161 | } | ||
162 | |||
163 | msg.cmd = TEGRA_VGPU_CMD_AS_MAP_EX; | ||
164 | msg.handle = vgpu_get_handle(g); | ||
165 | p->handle = vm->handle; | ||
166 | p->gpu_va = map_offset; | ||
167 | p->size = buffer_size; | ||
168 | p->mem_desc_count = mem_desc_count; | ||
169 | p->pgsz_idx = pgsz_idx; | ||
170 | p->iova = 0; | ||
171 | p->kind = kind_v; | ||
172 | if (flags & NVGPU_VM_MAP_CACHEABLE) | ||
173 | p->flags = TEGRA_VGPU_MAP_CACHEABLE; | ||
174 | if (flags & NVGPU_VM_MAP_IO_COHERENT) | ||
175 | p->flags |= TEGRA_VGPU_MAP_IO_COHERENT; | ||
176 | if (flags & NVGPU_VM_MAP_L3_ALLOC) | ||
177 | p->flags |= TEGRA_VGPU_MAP_L3_ALLOC; | ||
178 | p->prot = prot; | ||
179 | p->ctag_offset = ctag_offset; | ||
180 | p->clear_ctags = clear_ctags; | ||
181 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
182 | if (err || msg.ret) | ||
183 | goto fail; | ||
184 | |||
185 | /* TLB invalidate handled on server side */ | ||
186 | |||
187 | vgpu_ivc_oob_put_ptr(handle); | ||
188 | return map_offset; | ||
189 | fail: | ||
190 | if (handle) | ||
191 | vgpu_ivc_oob_put_ptr(handle); | ||
192 | nvgpu_err(g, "Failed: err=%d, msg.ret=%d", err, msg.ret); | ||
193 | nvgpu_err(g, | ||
194 | " Map: %-5s GPU virt %#-12llx +%#-9llx " | ||
195 | "phys offset: %#-4llx; pgsz: %3dkb perm=%-2s | " | ||
196 | "kind=%#02x APT=%-6s", | ||
197 | vm->name, map_offset, buffer_size, buffer_offset, | ||
198 | vm->gmmu_page_sizes[pgsz_idx] >> 10, | ||
199 | nvgpu_gmmu_perm_str(rw_flag), | ||
200 | kind_v, "SYSMEM"); | ||
201 | for (i = 0; i < mem_desc_count; i++) | ||
202 | nvgpu_err(g, " > 0x%010llx + 0x%llx", | ||
203 | mem_desc[i].addr, mem_desc[i].length); | ||
204 | |||
205 | return 0; | ||
206 | } | ||
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h new file mode 100644 index 00000000..44072dd6 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h | |||
@@ -0,0 +1,45 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef __VGPU_MM_GP10B_H__ | ||
24 | #define __VGPU_MM_GP10B_H__ | ||
25 | |||
26 | #include "gk20a/gk20a.h" | ||
27 | |||
28 | u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm, | ||
29 | u64 map_offset, | ||
30 | struct nvgpu_sgt *sgt, | ||
31 | u64 buffer_offset, | ||
32 | u64 size, | ||
33 | int pgsz_idx, | ||
34 | u8 kind_v, | ||
35 | u32 ctag_offset, | ||
36 | u32 flags, | ||
37 | int rw_flag, | ||
38 | bool clear_ctags, | ||
39 | bool sparse, | ||
40 | bool priv, | ||
41 | struct vm_gk20a_mapping_batch *batch, | ||
42 | enum nvgpu_aperture aperture); | ||
43 | int vgpu_gp10b_init_mm_setup_hw(struct gk20a *g); | ||
44 | |||
45 | #endif | ||