gpu: nvgpu: vgpu: support clk-arb

1. Implement the following vgpu functions to support clk-arb:
- vgpu_clk_get_range() to return min and max freqs from
supported frequencies
- implement vgpu_clk_get_round_rate() which sets rounded
rate to input rate. Rounding is handled in RM Server
- modify vgpu_clk_get_freqs() to retrieve freq table in IVM
memory instead of copying the value in array as part of cmd
message.

2. Add support for clk-arb related HALs for vgpu.

3. support_clk_freq_controller is assigned true for vgpu
provided guest VM has the privilege to set clock frequency.

Bug 200422845
Bug 2363882
Jira EVLR-3254

Change-Id: I91fc392db381c5db1d52b19d45ec0481fdc27554
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1812379
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 16 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
index 78aef699..2b4b3463 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -59,6 +59,7 @@
 #include "gp10b/gr_ctx_gp10b.h"
 #include "gp10b/fifo_gp10b.h"
 #include "gp10b/regops_gp10b.h"
+#include "gp10b/clk_arb_gp10b.h"
 
 #include "gm20b/gr_gm20b.h"
 #include "gm20b/fifo_gm20b.h"
@@ -450,6 +451,15 @@ static const struct gpu_ops vgpu_gp10b_ops = {
                 .reset_engine = NULL,
                 .is_engine_in_reset = NULL,
         },
+        .clk_arb = {
+                .get_arbiter_clk_domains = gp10b_get_arbiter_clk_domains,
+                .get_arbiter_f_points = gp10b_get_arbiter_f_points,
+                .get_arbiter_clk_range = gp10b_get_arbiter_clk_range,
+                .get_arbiter_clk_default = gp10b_get_arbiter_clk_default,
+                .arbiter_clk_init = gp10b_init_clk_arbiter,
+                .clk_arb_run_arbiter_cb = gp10b_clk_arb_run_arbiter_cb,
+                .clk_arb_cleanup = gp10b_clk_arb_cleanup,
+        },
         .regops = {
                 .exec_regops = vgpu_exec_regops,
                 .get_global_whitelist_ranges =
@@ -558,6 +568,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 int vgpu_gp10b_init_hal(struct gk20a *g)
 {
         struct gpu_ops *gops = &g->ops;
+        struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
 
         gops->ltc = vgpu_gp10b_ops.ltc;
         gops->ce2 = vgpu_gp10b_ops.ce2;
@@ -573,6 +584,7 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
         gops->pramin = vgpu_gp10b_ops.pramin;
         gops->therm = vgpu_gp10b_ops.therm;
         gops->pmu = vgpu_gp10b_ops.pmu;
+        gops->clk_arb = vgpu_gp10b_ops.clk_arb;
         gops->regops = vgpu_gp10b_ops.regops;
         gops->mc = vgpu_gp10b_ops.mc;
         gops->debug = vgpu_gp10b_ops.debug;
@@ -642,6 +654,10 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
         __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
         g->pmu_lsf_pmu_wpr_init_done = 0;
 
+        if (priv->constants.can_set_clkrate) {
+                gops->clk.support_clk_freq_controller = true;
+        }
+
         g->name = "gp10b";
 
         return 0;