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authorAingara Paramakuru <aparamakuru@nvidia.com>2015-11-03 11:44:14 -0500
committerDeepak Nibade <dnibade@nvidia.com>2016-12-27 04:52:09 -0500
commit9ab9436268ae2121d3dc57c98d16890953f6cd35 (patch)
treec499c00b1e563396e0dc577f359cc242016b7e3f /drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
parentf4b2a02b68d79d30a1292f9b3551d08c71fb899f (diff)
gpu: nvgpu: gp10b: map GfxP buffers as GPU cacheable
Some of the allocated buffers are used during normal graphics processing. Mark them as GPU cacheable to improve performance. Bug 1695718 Change-Id: I71d5d1538516e966526abe5e38a557776321597f Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/827087 (cherry picked from commit 60b40ac144c94e24a2c449c8be937edf8865e1ed) Reviewed-on: http://git-master/r/828493 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c21
1 files changed, 12 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
index 5edaa819..c5c53b58 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
@@ -84,9 +84,9 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g,
84 gk20a_dbg_info("gfxp context attrib cb size=%d", 84 gk20a_dbg_info("gfxp context attrib cb size=%d",
85 attrib_cb_size); 85 attrib_cb_size);
86 86
87 err = gk20a_gmmu_alloc_map(vm, 87 err = gr_gp10b_alloc_buffer(vm,
88 g->gr.t18x.ctx_vars.preempt_image_size, 88 g->gr.t18x.ctx_vars.preempt_image_size,
89 &gr_ctx->t18x.preempt_ctxsw_buffer); 89 &gr_ctx->t18x.preempt_ctxsw_buffer);
90 if (err) { 90 if (err) {
91 err = -ENOMEM; 91 err = -ENOMEM;
92 goto fail; 92 goto fail;
@@ -95,8 +95,9 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g,
95 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->gpu_va; 95 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->gpu_va;
96 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->size; 96 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->size;
97 97
98 err = gk20a_gmmu_alloc_map(vm, spill_size, 98 err = gr_gp10b_alloc_buffer(vm,
99 &gr_ctx->t18x.spill_ctxsw_buffer); 99 spill_size,
100 &gr_ctx->t18x.spill_ctxsw_buffer);
100 if (err) { 101 if (err) {
101 err = -ENOMEM; 102 err = -ENOMEM;
102 goto fail; 103 goto fail;
@@ -105,8 +106,9 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g,
105 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->gpu_va; 106 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->gpu_va;
106 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->size; 107 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->size;
107 108
108 err = gk20a_gmmu_alloc_map(vm, pagepool_size, 109 err = gr_gp10b_alloc_buffer(vm,
109 &gr_ctx->t18x.pagepool_ctxsw_buffer); 110 pagepool_size,
111 &gr_ctx->t18x.pagepool_ctxsw_buffer);
110 if (err) { 112 if (err) {
111 err = -ENOMEM; 113 err = -ENOMEM;
112 goto fail; 114 goto fail;
@@ -116,8 +118,9 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g,
116 desc->gpu_va; 118 desc->gpu_va;
117 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = desc->size; 119 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = desc->size;
118 120
119 err = gk20a_gmmu_alloc_map(vm, attrib_cb_size, 121 err = gr_gp10b_alloc_buffer(vm,
120 &gr_ctx->t18x.betacb_ctxsw_buffer); 122 attrib_cb_size,
123 &gr_ctx->t18x.betacb_ctxsw_buffer);
121 if (err) { 124 if (err) {
122 err = -ENOMEM; 125 err = -ENOMEM;
123 goto fail; 126 goto fail;