gpu: nvgpu: vgpu: flatten out vgpu hal

Instead of calling the native HAL init function then adding
multiple layers of modification for VGPU, flatten out the sequence
so that all entry points are set statically and visible in a
single file.

JIRA ESRM-30

Change-Id: Ie424abb48bce5038874851d399baac5e4bb7d27c
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1574616
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 5 insertions, 16 deletions

diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
index ec2fcd8e..fa6109ad 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
@@ -31,7 +31,7 @@
 
 #include <nvgpu/hw/gp10b/hw_gr_gp10b.h>
 
-static void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
+void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
                                 struct gr_ctx_desc *gr_ctx)
 {
         struct tegra_vgpu_cmd_msg msg = {0};
@@ -59,7 +59,7 @@ static void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
         nvgpu_kfree(g, gr_ctx);
 }
 
-static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g,
+int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g,
                                 struct gr_ctx_desc **__gr_ctx,
                                 struct vm_gk20a *vm,
                                 u32 class,
@@ -115,7 +115,7 @@ fail:
         return err;
 }
 
-static int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
+int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
                                 struct gr_ctx_desc *gr_ctx,
                                 struct vm_gk20a *vm, u32 class,
                                 u32 graphics_preempt_mode,
@@ -267,7 +267,7 @@ fail:
         return err;
 }
 
-static int vgpu_gr_gp10b_set_preemption_mode(struct channel_gk20a *ch,
+int vgpu_gr_gp10b_set_preemption_mode(struct channel_gk20a *ch,
                                         u32 graphics_preempt_mode,
                                         u32 compute_preempt_mode)
 {
@@ -316,7 +316,7 @@ static int vgpu_gr_gp10b_set_preemption_mode(struct channel_gk20a *ch,
         return err;
 }
 
-static int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g)
+int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g)
 {
         struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
         int err;
@@ -334,14 +334,3 @@ static int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g)
 
         return 0;
 }
-
-void vgpu_gp10b_init_gr_ops(struct gpu_ops *gops)
-{
-        vgpu_gm20b_init_gr_ops(gops);
-        gops->gr.alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx;
-        gops->gr.free_gr_ctx = vgpu_gr_gp10b_free_gr_ctx;
-        gops->gr.init_ctx_state = vgpu_gr_gp10b_init_ctx_state;
-        gops->gr.set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode;
-        gops->gr.set_ctxsw_preemption_mode =
-                        vgpu_gr_gp10b_set_ctxsw_preemption_mode;
-}