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authorDeepak Nibade <dnibade@nvidia.com>2017-11-14 09:43:28 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-11-17 11:27:19 -0500
commitb42fb7ba26b565f93118fbdd9e17b42ee6144c5e (patch)
tree26e2d919f019d15b51bba4d7b5c938f77ad5cff5 /drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c
parentb7cc3a2aa6c92a09eed43513287c9062f22ad127 (diff)
gpu: nvgpu: move vgpu code to linux
Most of VGPU code is linux specific but lies in common code So until VGPU code is properly abstracted and made os-independent, move all of VGPU code to linux specific directory Handle corresponding Makefile changes Update all #includes to reflect new paths Add GPL license to newly added linux files Jira NVGPU-387 Change-Id: Ic133e4c80e570bcc273f0dacf45283fefd678923 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1599472 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c588
1 files changed, 0 insertions, 588 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c
deleted file mode 100644
index a3eb59ac..00000000
--- a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c
+++ /dev/null
@@ -1,588 +0,0 @@
1/*
2 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include "gm20b/hal_gm20b.h"
24#include "vgpu/vgpu.h"
25#include "vgpu/fifo_vgpu.h"
26#include "vgpu/gr_vgpu.h"
27#include "vgpu/ltc_vgpu.h"
28#include "vgpu/mm_vgpu.h"
29#include "vgpu/dbg_vgpu.h"
30#include "vgpu/fecs_trace_vgpu.h"
31#include "vgpu/css_vgpu.h"
32#include "vgpu_gr_gm20b.h"
33
34#include "gk20a/bus_gk20a.h"
35#include "gk20a/flcn_gk20a.h"
36#include "gk20a/mc_gk20a.h"
37#include "gk20a/fb_gk20a.h"
38
39#include "gm20b/gr_gm20b.h"
40#include "gm20b/fifo_gm20b.h"
41#include "gm20b/acr_gm20b.h"
42#include "gm20b/pmu_gm20b.h"
43#include "gm20b/fb_gm20b.h"
44#include "gm20b/bus_gm20b.h"
45#include "gm20b/regops_gm20b.h"
46#include "gm20b/clk_gm20b.h"
47#include "gm20b/therm_gm20b.h"
48#include "gm20b/mm_gm20b.h"
49#include "gm20b/gr_ctx_gm20b.h"
50#include "gm20b/gm20b_gating_reglist.h"
51#include "gm20b/ltc_gm20b.h"
52
53#include <nvgpu/enabled.h>
54
55#include <nvgpu/hw/gm20b/hw_fuse_gm20b.h>
56#include <nvgpu/hw/gm20b/hw_pwr_gm20b.h>
57#include <nvgpu/hw/gm20b/hw_fifo_gm20b.h>
58#include <nvgpu/hw/gm20b/hw_ram_gm20b.h>
59
60static const struct gpu_ops vgpu_gm20b_ops = {
61 .ltc = {
62 .determine_L2_size_bytes = vgpu_determine_L2_size_bytes,
63 .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
64 .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry,
65 .init_cbc = gm20b_ltc_init_cbc,
66 .init_fs_state = vgpu_ltc_init_fs_state,
67 .init_comptags = vgpu_ltc_init_comptags,
68 .cbc_ctrl = NULL,
69 .isr = gm20b_ltc_isr,
70 .cbc_fix_config = gm20b_ltc_cbc_fix_config,
71 .flush = gm20b_flush_ltc,
72 .set_enabled = gm20b_ltc_set_enabled,
73 },
74 .ce2 = {
75 .isr_stall = gk20a_ce2_isr,
76 .isr_nonstall = gk20a_ce2_nonstall_isr,
77 .get_num_pce = vgpu_ce_get_num_pce,
78 },
79 .gr = {
80 .get_patch_slots = gr_gk20a_get_patch_slots,
81 .init_gpc_mmu = gr_gm20b_init_gpc_mmu,
82 .bundle_cb_defaults = gr_gm20b_bundle_cb_defaults,
83 .cb_size_default = gr_gm20b_cb_size_default,
84 .calc_global_ctx_buffer_size =
85 gr_gm20b_calc_global_ctx_buffer_size,
86 .commit_global_attrib_cb = gr_gm20b_commit_global_attrib_cb,
87 .commit_global_bundle_cb = gr_gm20b_commit_global_bundle_cb,
88 .commit_global_cb_manager = gr_gm20b_commit_global_cb_manager,
89 .commit_global_pagepool = gr_gm20b_commit_global_pagepool,
90 .handle_sw_method = gr_gm20b_handle_sw_method,
91 .set_alpha_circular_buffer_size =
92 gr_gm20b_set_alpha_circular_buffer_size,
93 .set_circular_buffer_size = gr_gm20b_set_circular_buffer_size,
94 .enable_hww_exceptions = gr_gk20a_enable_hww_exceptions,
95 .is_valid_class = gr_gm20b_is_valid_class,
96 .is_valid_gfx_class = gr_gm20b_is_valid_gfx_class,
97 .is_valid_compute_class = gr_gm20b_is_valid_compute_class,
98 .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs,
99 .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs,
100 .init_fs_state = vgpu_gm20b_init_fs_state,
101 .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask,
102 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
103 .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
104 .set_gpc_tpc_mask = gr_gm20b_set_gpc_tpc_mask,
105 .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask,
106 .free_channel_ctx = vgpu_gr_free_channel_ctx,
107 .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx,
108 .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull,
109 .get_zcull_info = vgpu_gr_get_zcull_info,
110 .is_tpc_addr = gr_gm20b_is_tpc_addr,
111 .get_tpc_num = gr_gm20b_get_tpc_num,
112 .detect_sm_arch = vgpu_gr_detect_sm_arch,
113 .add_zbc_color = gr_gk20a_add_zbc_color,
114 .add_zbc_depth = gr_gk20a_add_zbc_depth,
115 .zbc_set_table = vgpu_gr_add_zbc,
116 .zbc_query_table = vgpu_gr_query_zbc,
117 .pmu_save_zbc = gk20a_pmu_save_zbc,
118 .add_zbc = gr_gk20a_add_zbc,
119 .pagepool_default_size = gr_gm20b_pagepool_default_size,
120 .init_ctx_state = vgpu_gr_init_ctx_state,
121 .alloc_gr_ctx = vgpu_gr_alloc_gr_ctx,
122 .free_gr_ctx = vgpu_gr_free_gr_ctx,
123 .update_ctxsw_preemption_mode =
124 gr_gm20b_update_ctxsw_preemption_mode,
125 .dump_gr_regs = NULL,
126 .update_pc_sampling = gr_gm20b_update_pc_sampling,
127 .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask,
128 .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp,
129 .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc,
130 .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask,
131 .get_max_fbps_count = vgpu_gr_get_max_fbps_count,
132 .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info,
133 .wait_empty = gr_gk20a_wait_idle,
134 .init_cyclestats = vgpu_gr_gm20b_init_cyclestats,
135 .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode,
136 .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
137 .bpt_reg_info = gr_gm20b_bpt_reg_info,
138 .get_access_map = gr_gm20b_get_access_map,
139 .handle_fecs_error = gk20a_gr_handle_fecs_error,
140 .handle_sm_exception = gr_gk20a_handle_sm_exception,
141 .handle_tex_exception = gr_gk20a_handle_tex_exception,
142 .enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions,
143 .enable_exceptions = gk20a_gr_enable_exceptions,
144 .get_lrf_tex_ltc_dram_override = NULL,
145 .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode,
146 .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode,
147 .record_sm_error_state = gm20b_gr_record_sm_error_state,
148 .update_sm_error_state = gm20b_gr_update_sm_error_state,
149 .clear_sm_error_state = vgpu_gr_clear_sm_error_state,
150 .suspend_contexts = vgpu_gr_suspend_contexts,
151 .resume_contexts = vgpu_gr_resume_contexts,
152 .get_preemption_mode_flags = gr_gm20b_get_preemption_mode_flags,
153 .init_sm_id_table = gr_gk20a_init_sm_id_table,
154 .load_smid_config = gr_gm20b_load_smid_config,
155 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,
156 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
157 .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
158 .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
159 .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
160 .setup_rop_mapping = gr_gk20a_setup_rop_mapping,
161 .program_zcull_mapping = gr_gk20a_program_zcull_mapping,
162 .commit_global_timeslice = gr_gk20a_commit_global_timeslice,
163 .commit_inst = vgpu_gr_commit_inst,
164 .write_zcull_ptr = gr_gk20a_write_zcull_ptr,
165 .write_pm_ptr = gr_gk20a_write_pm_ptr,
166 .init_elcg_mode = gr_gk20a_init_elcg_mode,
167 .load_tpc_mask = gr_gm20b_load_tpc_mask,
168 .inval_icache = gr_gk20a_inval_icache,
169 .trigger_suspend = gr_gk20a_trigger_suspend,
170 .wait_for_pause = gr_gk20a_wait_for_pause,
171 .resume_from_pause = gr_gk20a_resume_from_pause,
172 .clear_sm_errors = gr_gk20a_clear_sm_errors,
173 .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions,
174 .get_esr_sm_sel = gk20a_gr_get_esr_sm_sel,
175 .sm_debugger_attached = gk20a_gr_sm_debugger_attached,
176 .suspend_single_sm = gk20a_gr_suspend_single_sm,
177 .suspend_all_sms = gk20a_gr_suspend_all_sms,
178 .resume_single_sm = gk20a_gr_resume_single_sm,
179 .resume_all_sms = gk20a_gr_resume_all_sms,
180 .get_sm_hww_warp_esr = gk20a_gr_get_sm_hww_warp_esr,
181 .get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr,
182 .get_sm_no_lock_down_hww_global_esr_mask =
183 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask,
184 .lock_down_sm = gk20a_gr_lock_down_sm,
185 .wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down,
186 .clear_sm_hww = gm20b_gr_clear_sm_hww,
187 .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf,
188 .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs,
189 .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
190 .init_ctxsw_hdr_data = gk20a_gr_init_ctxsw_hdr_data,
191 .set_boosted_ctx = NULL,
192 .update_boosted_ctx = NULL,
193 },
194 .fb = {
195 .reset = fb_gk20a_reset,
196 .init_hw = gk20a_fb_init_hw,
197 .init_fs_state = fb_gm20b_init_fs_state,
198 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
199 .set_use_full_comp_tag_line =
200 gm20b_fb_set_use_full_comp_tag_line,
201 .compression_page_size = gm20b_fb_compression_page_size,
202 .compressible_page_size = gm20b_fb_compressible_page_size,
203 .vpr_info_fetch = gm20b_fb_vpr_info_fetch,
204 .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info,
205 .read_wpr_info = gm20b_fb_read_wpr_info,
206 .is_debug_mode_enabled = NULL,
207 .set_debug_mode = vgpu_mm_mmu_set_debug_mode,
208 .tlb_invalidate = vgpu_mm_tlb_invalidate,
209 },
210 .clock_gating = {
211 .slcg_bus_load_gating_prod =
212 gm20b_slcg_bus_load_gating_prod,
213 .slcg_ce2_load_gating_prod =
214 gm20b_slcg_ce2_load_gating_prod,
215 .slcg_chiplet_load_gating_prod =
216 gm20b_slcg_chiplet_load_gating_prod,
217 .slcg_ctxsw_firmware_load_gating_prod =
218 gm20b_slcg_ctxsw_firmware_load_gating_prod,
219 .slcg_fb_load_gating_prod =
220 gm20b_slcg_fb_load_gating_prod,
221 .slcg_fifo_load_gating_prod =
222 gm20b_slcg_fifo_load_gating_prod,
223 .slcg_gr_load_gating_prod =
224 gr_gm20b_slcg_gr_load_gating_prod,
225 .slcg_ltc_load_gating_prod =
226 ltc_gm20b_slcg_ltc_load_gating_prod,
227 .slcg_perf_load_gating_prod =
228 gm20b_slcg_perf_load_gating_prod,
229 .slcg_priring_load_gating_prod =
230 gm20b_slcg_priring_load_gating_prod,
231 .slcg_pmu_load_gating_prod =
232 gm20b_slcg_pmu_load_gating_prod,
233 .slcg_therm_load_gating_prod =
234 gm20b_slcg_therm_load_gating_prod,
235 .slcg_xbar_load_gating_prod =
236 gm20b_slcg_xbar_load_gating_prod,
237 .blcg_bus_load_gating_prod =
238 gm20b_blcg_bus_load_gating_prod,
239 .blcg_ctxsw_firmware_load_gating_prod =
240 gm20b_blcg_ctxsw_firmware_load_gating_prod,
241 .blcg_fb_load_gating_prod =
242 gm20b_blcg_fb_load_gating_prod,
243 .blcg_fifo_load_gating_prod =
244 gm20b_blcg_fifo_load_gating_prod,
245 .blcg_gr_load_gating_prod =
246 gm20b_blcg_gr_load_gating_prod,
247 .blcg_ltc_load_gating_prod =
248 gm20b_blcg_ltc_load_gating_prod,
249 .blcg_pwr_csb_load_gating_prod =
250 gm20b_blcg_pwr_csb_load_gating_prod,
251 .blcg_xbar_load_gating_prod =
252 gm20b_blcg_xbar_load_gating_prod,
253 .blcg_pmu_load_gating_prod =
254 gm20b_blcg_pmu_load_gating_prod,
255 .pg_gr_load_gating_prod =
256 gr_gm20b_pg_gr_load_gating_prod,
257 },
258 .fifo = {
259 .init_fifo_setup_hw = vgpu_init_fifo_setup_hw,
260 .bind_channel = vgpu_channel_bind,
261 .unbind_channel = vgpu_channel_unbind,
262 .disable_channel = vgpu_channel_disable,
263 .enable_channel = vgpu_channel_enable,
264 .alloc_inst = vgpu_channel_alloc_inst,
265 .free_inst = vgpu_channel_free_inst,
266 .setup_ramfc = vgpu_channel_setup_ramfc,
267 .channel_set_timeslice = vgpu_channel_set_timeslice,
268 .default_timeslice_us = vgpu_fifo_default_timeslice_us,
269 .setup_userd = gk20a_fifo_setup_userd,
270 .userd_gp_get = gk20a_fifo_userd_gp_get,
271 .userd_gp_put = gk20a_fifo_userd_gp_put,
272 .userd_pb_get = gk20a_fifo_userd_pb_get,
273 .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
274 .preempt_channel = vgpu_fifo_preempt_channel,
275 .preempt_tsg = vgpu_fifo_preempt_tsg,
276 .enable_tsg = vgpu_enable_tsg,
277 .disable_tsg = gk20a_disable_tsg,
278 .tsg_verify_channel_status = NULL,
279 .tsg_verify_status_ctx_reload = NULL,
280 .update_runlist = vgpu_fifo_update_runlist,
281 .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault,
282 .get_mmu_fault_info = gk20a_fifo_get_mmu_fault_info,
283 .wait_engine_idle = vgpu_fifo_wait_engine_idle,
284 .get_num_fifos = gm20b_fifo_get_num_fifos,
285 .get_pbdma_signature = gk20a_fifo_get_pbdma_signature,
286 .set_runlist_interleave = vgpu_fifo_set_runlist_interleave,
287 .tsg_set_timeslice = vgpu_tsg_set_timeslice,
288 .tsg_open = vgpu_tsg_open,
289 .force_reset_ch = vgpu_fifo_force_reset_ch,
290 .engine_enum_from_type = gk20a_fifo_engine_enum_from_type,
291 .device_info_data_parse = gm20b_device_info_data_parse,
292 .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v,
293 .init_engine_info = vgpu_fifo_init_engine_info,
294 .runlist_entry_size = ram_rl_entry_size_v,
295 .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry,
296 .get_ch_runlist_entry = gk20a_get_ch_runlist_entry,
297 .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc,
298 .dump_pbdma_status = gk20a_dump_pbdma_status,
299 .dump_eng_status = gk20a_dump_eng_status,
300 .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc,
301 .intr_0_error_mask = gk20a_fifo_intr_0_error_mask,
302 .is_preempt_pending = gk20a_fifo_is_preempt_pending,
303 .init_pbdma_intr_descs = gm20b_fifo_init_pbdma_intr_descs,
304 .reset_enable_hw = gk20a_init_fifo_reset_enable_hw,
305 .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg,
306 .handle_sched_error = gk20a_fifo_handle_sched_error,
307 .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0,
308 .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1,
309 .tsg_bind_channel = vgpu_tsg_bind_channel,
310 .tsg_unbind_channel = vgpu_tsg_unbind_channel,
311#ifdef CONFIG_TEGRA_GK20A_NVHOST
312 .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
313 .free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
314 .add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd,
315 .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size,
316 .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd,
317 .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size,
318#endif
319 },
320 .gr_ctx = {
321 .get_netlist_name = gr_gm20b_get_netlist_name,
322 .is_fw_defined = gr_gm20b_is_firmware_defined,
323 },
324 .mm = {
325 .support_sparse = gm20b_mm_support_sparse,
326 .gmmu_map = vgpu_locked_gmmu_map,
327 .gmmu_unmap = vgpu_locked_gmmu_unmap,
328 .vm_bind_channel = vgpu_vm_bind_channel,
329 .fb_flush = vgpu_mm_fb_flush,
330 .l2_invalidate = vgpu_mm_l2_invalidate,
331 .l2_flush = vgpu_mm_l2_flush,
332 .cbc_clean = gk20a_mm_cbc_clean,
333 .set_big_page_size = gm20b_mm_set_big_page_size,
334 .get_big_page_sizes = gm20b_mm_get_big_page_sizes,
335 .get_default_big_page_size = gm20b_mm_get_default_big_page_size,
336 .gpu_phys_addr = gm20b_gpu_phys_addr,
337 .get_iommu_bit = gk20a_mm_get_iommu_bit,
338 .get_mmu_levels = gk20a_mm_get_mmu_levels,
339 .init_pdb = gk20a_mm_init_pdb,
340 .init_mm_setup_hw = NULL,
341 .is_bar1_supported = gm20b_mm_is_bar1_supported,
342 .init_inst_block = gk20a_init_inst_block,
343 .mmu_fault_pending = gk20a_fifo_mmu_fault_pending,
344 .get_kind_invalid = gm20b_get_kind_invalid,
345 .get_kind_pitch = gm20b_get_kind_pitch,
346 },
347 .therm = {
348 .init_therm_setup_hw = gm20b_init_therm_setup_hw,
349 .elcg_init_idle_filters = gk20a_elcg_init_idle_filters,
350 },
351 .pmu = {
352 .pmu_setup_elpg = gm20b_pmu_setup_elpg,
353 .pmu_get_queue_head = pwr_pmu_queue_head_r,
354 .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v,
355 .pmu_get_queue_tail = pwr_pmu_queue_tail_r,
356 .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v,
357 .pmu_queue_head = gk20a_pmu_queue_head,
358 .pmu_queue_tail = gk20a_pmu_queue_tail,
359 .pmu_msgq_tail = gk20a_pmu_msgq_tail,
360 .pmu_mutex_size = pwr_pmu_mutex__size_1_v,
361 .pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
362 .pmu_mutex_release = gk20a_pmu_mutex_release,
363 .write_dmatrfbase = gm20b_write_dmatrfbase,
364 .pmu_elpg_statistics = gk20a_pmu_elpg_statistics,
365 .pmu_pg_init_param = NULL,
366 .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list,
367 .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list,
368 .pmu_is_lpwr_feature_supported = NULL,
369 .pmu_lpwr_enable_pg = NULL,
370 .pmu_lpwr_disable_pg = NULL,
371 .pmu_pg_param_post_init = NULL,
372 .dump_secure_fuses = pmu_dump_security_fuses_gm20b,
373 .reset_engine = gk20a_pmu_engine_reset,
374 .is_engine_in_reset = gk20a_pmu_is_engine_in_reset,
375 },
376 .clk = {
377 .init_clk_support = gm20b_init_clk_support,
378 .suspend_clk_support = gm20b_suspend_clk_support,
379#ifdef CONFIG_DEBUG_FS
380 .init_debugfs = gm20b_clk_init_debugfs,
381#endif
382 .get_voltage = gm20b_clk_get_voltage,
383 .get_gpcclk_clock_counter = gm20b_clk_get_gpcclk_clock_counter,
384 .pll_reg_write = gm20b_clk_pll_reg_write,
385 .get_pll_debug_data = gm20b_clk_get_pll_debug_data,
386 },
387 .regops = {
388 .get_global_whitelist_ranges =
389 gm20b_get_global_whitelist_ranges,
390 .get_global_whitelist_ranges_count =
391 gm20b_get_global_whitelist_ranges_count,
392 .get_context_whitelist_ranges =
393 gm20b_get_context_whitelist_ranges,
394 .get_context_whitelist_ranges_count =
395 gm20b_get_context_whitelist_ranges_count,
396 .get_runcontrol_whitelist = gm20b_get_runcontrol_whitelist,
397 .get_runcontrol_whitelist_count =
398 gm20b_get_runcontrol_whitelist_count,
399 .get_runcontrol_whitelist_ranges =
400 gm20b_get_runcontrol_whitelist_ranges,
401 .get_runcontrol_whitelist_ranges_count =
402 gm20b_get_runcontrol_whitelist_ranges_count,
403 .get_qctl_whitelist = gm20b_get_qctl_whitelist,
404 .get_qctl_whitelist_count = gm20b_get_qctl_whitelist_count,
405 .get_qctl_whitelist_ranges = gm20b_get_qctl_whitelist_ranges,
406 .get_qctl_whitelist_ranges_count =
407 gm20b_get_qctl_whitelist_ranges_count,
408 .apply_smpc_war = gm20b_apply_smpc_war,
409 },
410 .mc = {
411 .intr_enable = mc_gk20a_intr_enable,
412 .intr_unit_config = mc_gk20a_intr_unit_config,
413 .isr_stall = mc_gk20a_isr_stall,
414 .intr_stall = mc_gk20a_intr_stall,
415 .intr_stall_pause = mc_gk20a_intr_stall_pause,
416 .intr_stall_resume = mc_gk20a_intr_stall_resume,
417 .intr_nonstall = mc_gk20a_intr_nonstall,
418 .intr_nonstall_pause = mc_gk20a_intr_nonstall_pause,
419 .intr_nonstall_resume = mc_gk20a_intr_nonstall_resume,
420 .enable = gk20a_mc_enable,
421 .disable = gk20a_mc_disable,
422 .reset = gk20a_mc_reset,
423 .boot_0 = gk20a_mc_boot_0,
424 .is_intr1_pending = mc_gk20a_is_intr1_pending,
425 },
426 .debug = {
427 .show_dump = NULL,
428 },
429 .dbg_session_ops = {
430 .exec_reg_ops = vgpu_exec_regops,
431 .dbg_set_powergate = vgpu_dbg_set_powergate,
432 .check_and_set_global_reservation =
433 vgpu_check_and_set_global_reservation,
434 .check_and_set_context_reservation =
435 vgpu_check_and_set_context_reservation,
436 .release_profiler_reservation =
437 vgpu_release_profiler_reservation,
438 .perfbuffer_enable = vgpu_perfbuffer_enable,
439 .perfbuffer_disable = vgpu_perfbuffer_disable,
440 },
441 .bus = {
442 .init_hw = gk20a_bus_init_hw,
443 .isr = gk20a_bus_isr,
444 .read_ptimer = vgpu_read_ptimer,
445 .get_timestamps_zipper = vgpu_get_timestamps_zipper,
446 .bar1_bind = gm20b_bus_bar1_bind,
447 },
448#if defined(CONFIG_GK20A_CYCLE_STATS)
449 .css = {
450 .enable_snapshot = vgpu_css_enable_snapshot_buffer,
451 .disable_snapshot = vgpu_css_release_snapshot_buffer,
452 .check_data_available = vgpu_css_flush_snapshots,
453 .detach_snapshot = vgpu_css_detach,
454 .set_handled_snapshots = NULL,
455 .allocate_perfmon_ids = NULL,
456 .release_perfmon_ids = NULL,
457 },
458#endif
459 .falcon = {
460 .falcon_hal_sw_init = gk20a_falcon_hal_sw_init,
461 },
462 .priv_ring = {
463 .isr = gk20a_priv_ring_isr,
464 },
465 .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics,
466 .get_litter_value = gm20b_get_litter_value,
467};
468
469int vgpu_gm20b_init_hal(struct gk20a *g)
470{
471 struct gpu_ops *gops = &g->ops;
472 u32 val;
473
474 gops->ltc = vgpu_gm20b_ops.ltc;
475 gops->ce2 = vgpu_gm20b_ops.ce2;
476 gops->gr = vgpu_gm20b_ops.gr;
477 gops->fb = vgpu_gm20b_ops.fb;
478 gops->clock_gating = vgpu_gm20b_ops.clock_gating;
479 gops->fifo = vgpu_gm20b_ops.fifo;
480 gops->gr_ctx = vgpu_gm20b_ops.gr_ctx;
481 gops->mm = vgpu_gm20b_ops.mm;
482 gops->therm = vgpu_gm20b_ops.therm;
483 gops->pmu = vgpu_gm20b_ops.pmu;
484 /*
485 * clk must be assigned member by member
486 * since some clk ops are assigned during probe prior to HAL init
487 */
488 gops->clk.init_clk_support = vgpu_gm20b_ops.clk.init_clk_support;
489 gops->clk.suspend_clk_support = vgpu_gm20b_ops.clk.suspend_clk_support;
490 gops->clk.get_voltage = vgpu_gm20b_ops.clk.get_voltage;
491 gops->clk.get_gpcclk_clock_counter =
492 vgpu_gm20b_ops.clk.get_gpcclk_clock_counter;
493 gops->clk.pll_reg_write = vgpu_gm20b_ops.clk.pll_reg_write;
494 gops->clk.get_pll_debug_data = vgpu_gm20b_ops.clk.get_pll_debug_data;
495
496 gops->regops = vgpu_gm20b_ops.regops;
497 gops->mc = vgpu_gm20b_ops.mc;
498 gops->dbg_session_ops = vgpu_gm20b_ops.dbg_session_ops;
499 gops->debug = vgpu_gm20b_ops.debug;
500 gops->bus = vgpu_gm20b_ops.bus;
501#if defined(CONFIG_GK20A_CYCLE_STATS)
502 gops->css = vgpu_gm20b_ops.css;
503#endif
504 gops->falcon = vgpu_gm20b_ops.falcon;
505
506 gops->priv_ring = vgpu_gm20b_ops.priv_ring;
507
508 /* Lone functions */
509 gops->chip_init_gpu_characteristics =
510 vgpu_gm20b_ops.chip_init_gpu_characteristics;
511 gops->get_litter_value = vgpu_gm20b_ops.get_litter_value;
512
513 __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
514 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
515 __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
516
517#ifdef CONFIG_TEGRA_ACR
518 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
519 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
520 } else {
521 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
522 if (!val) {
523 gk20a_dbg_info("priv security is disabled in HW");
524 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
525 } else {
526 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
527 }
528 }
529#else
530 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
531 gk20a_dbg_info("running ASIM with PRIV security disabled");
532 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
533 } else {
534 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
535 if (!val) {
536 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
537 } else {
538 gk20a_dbg_info("priv security is not supported but enabled");
539 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
540 return -EPERM;
541 }
542 }
543#endif
544
545 /* priv security dependent ops */
546 if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
547 /* Add in ops from gm20b acr */
548 gops->pmu.is_pmu_supported = gm20b_is_pmu_supported;
549 gops->pmu.prepare_ucode = prepare_ucode_blob;
550 gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn;
551 gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap;
552 gops->pmu.is_priv_load = gm20b_is_priv_load;
553 gops->pmu.get_wpr = gm20b_wpr_info;
554 gops->pmu.alloc_blob_space = gm20b_alloc_blob_space;
555 gops->pmu.pmu_populate_loader_cfg =
556 gm20b_pmu_populate_loader_cfg;
557 gops->pmu.flcn_populate_bl_dmem_desc =
558 gm20b_flcn_populate_bl_dmem_desc;
559 gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt;
560 gops->pmu.falcon_clear_halt_interrupt_status =
561 clear_halt_interrupt_status;
562 gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1;
563
564 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
565 gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode;
566
567 gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode;
568 } else {
569 /* Inherit from gk20a */
570 gops->pmu.is_pmu_supported = gk20a_is_pmu_supported;
571 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob;
572 gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1;
573 gops->pmu.pmu_nsbootstrap = pmu_bootstrap;
574
575 gops->pmu.load_lsfalcon_ucode = NULL;
576 gops->pmu.init_wpr_region = NULL;
577
578 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
579 }
580
581 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
582 g->pmu_lsf_pmu_wpr_init_done = 0;
583 g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
584
585 g->name = "gm20b";
586
587 return 0;
588}
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-04 22:39:40 -0400