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authorPeter Daifuku <pdaifuku@nvidia.com>2016-03-31 17:57:20 -0400
committerTerje Bergstrom <tbergstrom@nvidia.com>2016-05-20 16:38:13 -0400
commita21e56d584641202327f64741b06b1cd9633d0f6 (patch)
treee52766b071ec539f95b0fb5da459a8d015a830d1 /drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.c
parentce0fe5082ebb8a7e0ca5a8992e17ae4547d4db5e (diff)
gpu: nvgpu: vgpu: add support for VSM ioctls
Add virtualized support for NUM_VSMS and VSMS_MAPPING ioctls. This requires adding an attribute request for the RM server, GPC0_TPC_COUNT JIRASW EVLR-253 Change-Id: Icaab4fadbbc9eab5d00cf78132928686944162df Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1130615 (cherry picked from commit 78514079382b0de48457db340e3479e99a012040) Reviewed-on: http://git-master/r/1133865 (cherry picked from commit 27a8e645e2787a43d0073f0be6e8f64c0f183228) Reviewed-on: http://git-master/r/1122553 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.c25
1 files changed, 24 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.c b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.c
index 07d41b2e..fb1f31d8 100644
--- a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.c
+++ b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -37,7 +37,30 @@ static void vgpu_gm20b_detect_sm_arch(struct gk20a *g)
37 gr_gpc0_tpc0_sm_arch_warp_count_v(v); 37 gr_gpc0_tpc0_sm_arch_warp_count_v(v);
38} 38}
39 39
40static int vgpu_gm20b_init_fs_state(struct gk20a *g)
41{
42 struct gr_gk20a *gr = &g->gr;
43 u32 tpc_index, gpc_index;
44 u32 sm_id = 0;
45
46 gk20a_dbg_fn("");
47
48 for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) {
49 for (tpc_index = 0; tpc_index < gr->gpc_tpc_count[gpc_index];
50 tpc_index++) {
51 g->gr.sm_to_cluster[sm_id].tpc_index = tpc_index;
52 g->gr.sm_to_cluster[sm_id].gpc_index = gpc_index;
53
54 sm_id++;
55 }
56 }
57
58 gr->no_of_sm = sm_id;
59 return 0;
60}
61
40void vgpu_gm20b_init_gr_ops(struct gpu_ops *gops) 62void vgpu_gm20b_init_gr_ops(struct gpu_ops *gops)
41{ 63{
42 gops->gr.detect_sm_arch = vgpu_gm20b_detect_sm_arch; 64 gops->gr.detect_sm_arch = vgpu_gm20b_detect_sm_arch;
65 gops->gr.init_fs_state = vgpu_gm20b_init_fs_state;
43} 66}