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| author | Seema Khowala <seemaj@nvidia.com> | 2017-02-16 19:53:35 -0500 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-04-12 18:33:50 -0400 |
| commit | c3c3a3c5715d6aa38544922b76a636135429fd22 (patch) | |
| tree | 4e608ad8e817229ff088cad2f2ddb3606f39b73e /drivers/gpu/nvgpu/vgpu/gk20a | |
| parent | 3867db86bce819901e566ac46ea5cd1ead3dad11 (diff) | |
gpu: nvgpu: add fifo ops for handling pbdma intr_0
This is needed to handle bit 20 (clear_faulted_error) and
bit 24 (eng_reset) of t19x pbdma_intr_0 interrupt.
JIRA GPUT19X-47
Change-Id: I07c603eff96344c0104579e339e5cf7f675128ef
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1306556
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/gk20a')
0 files changed, 0 insertions, 0 deletions