gpu: nvgpu: vgpu: add support for VSM ioctls

Add virtualized support for NUM_VSMS and VSMS_MAPPING ioctls.

This requires adding an attribute request for the RM server, GPC0_TPC_COUNT

JIRASW EVLR-253

Change-Id: Icaab4fadbbc9eab5d00cf78132928686944162df
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1130615
(cherry picked from commit 78514079382b0de48457db340e3479e99a012040)
Reviewed-on: http://git-master/r/1133865
(cherry picked from commit 27a8e645e2787a43d0073f0be6e8f64c0f183228)
Reviewed-on: http://git-master/r/1122553
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 29 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/vgpu/gk20a/vgpu_gr_gk20a.c b/drivers/gpu/nvgpu/vgpu/gk20a/vgpu_gr_gk20a.c
index 0a2ca743..2cfe16da 100644
--- a/drivers/gpu/nvgpu/vgpu/gk20a/vgpu_gr_gk20a.c
+++ b/drivers/gpu/nvgpu/vgpu/gk20a/vgpu_gr_gk20a.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015-2016, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -45,7 +45,35 @@ static void vgpu_gk20a_detect_sm_arch(struct gk20a *g)
                 gr_gpc0_tpc0_sm_arch_warp_count_v(v);
 }
 
+static int vgpu_gk20a_init_fs_state(struct gk20a *g)
+{
+        struct gr_gk20a *gr = &g->gr;
+        u32 tpc_index, gpc_index;
+        u32 sm_id = 0;
+
+        gk20a_dbg_fn("");
+
+        for (tpc_index = 0; tpc_index < gr->max_tpc_per_gpc_count;
+                tpc_index++) {
+                for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) {
+                        if (tpc_index < gr->gpc_tpc_count[gpc_index]) {
+                                g->gr.sm_to_cluster[sm_id].tpc_index =
+                                                                tpc_index;
+                                g->gr.sm_to_cluster[sm_id].gpc_index =
+                                                                gpc_index;
+
+                                sm_id++;
+                        }
+                }
+        }
+
+        gr->no_of_sm = sm_id;
+
+        return 0;
+}
+
 void vgpu_gk20a_init_gr_ops(struct gpu_ops *gops)
 {
         gops->gr.detect_sm_arch = vgpu_gk20a_detect_sm_arch;
+        gops->gr.init_fs_state = vgpu_gk20a_init_fs_state;
 }