summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h
diff options
context:
space:
mode:
authorDebarshi Dutta <ddutta@nvidia.com>2018-11-30 00:27:05 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2019-02-11 11:18:47 -0500
commit18643ac1357a845d204d6dabd98359a0ab0509a7 (patch)
treec04d1f18668eb0fafae7c345780db52d5064d185 /drivers/gpu/nvgpu/vgpu/fifo_vgpu.h
parenta8f0cb89f423093c334202dcfe43cb5729efca85 (diff)
gpu: nvgpu: replace input param chid with pointer to channel
preempt_channel needs to use the channel to pass it to other public functions, get access to a tsg etc. This qualifies it to take a pointer to a channel as an input parameter instead of a chid. Increment the channel ref counter using the function gk20a_channel_from_id in functions where we get the chid from the h/w registers directly. Once the prempt_channel function call is done, use a gk20a_channel_put on the referenced channel. Jira NVGPU-1461 Change-Id: I6c87c8104cfcb418d468c8c590087fd4aeabf4bd Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1963200 (cherry picked from commit 9abe9fe062367902ede7721cff55396859f8e4e8 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2013728 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/fifo_vgpu.h')
-rw-r--r--drivers/gpu/nvgpu/vgpu/fifo_vgpu.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h
index 8c042033..db199f8f 100644
--- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h
+++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h
@@ -41,7 +41,7 @@ int vgpu_channel_setup_ramfc(struct channel_gk20a *ch, u64 gpfifo_base,
41 u32 gpfifo_entries, 41 u32 gpfifo_entries,
42 unsigned long acquire_timeout, u32 flags); 42 unsigned long acquire_timeout, u32 flags);
43int vgpu_fifo_init_engine_info(struct fifo_gk20a *f); 43int vgpu_fifo_init_engine_info(struct fifo_gk20a *f);
44int vgpu_fifo_preempt_channel(struct gk20a *g, u32 chid); 44int vgpu_fifo_preempt_channel(struct gk20a *g, struct channel_gk20a *ch);
45int vgpu_fifo_preempt_tsg(struct gk20a *g, struct tsg_gk20a *tsg); 45int vgpu_fifo_preempt_tsg(struct gk20a *g, struct tsg_gk20a *tsg);
46int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id, 46int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id,
47 u32 chid, bool add, bool wait_for_finish); 47 u32 chid, bool add, bool wait_for_finish);