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authorAingara Paramakuru <aparamakuru@nvidia.com>2015-10-05 20:56:17 -0400
committerTerje Bergstrom <tbergstrom@nvidia.com>2015-10-22 10:40:08 -0400
commitfb3a1d31cd84771b659050ea1aa920bdf06ffb04 (patch)
treebfc6ee985d685353c41720cca252d2b9ab4fa86c /drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
parentee18a3ae2699513ab3762757432355b5624ce4a0 (diff)
gpu: nvgpu: vgpu: fix notification handling
Take a channel ref when handling a notification from the server, to prevent the channel from being closed. Also, mark the channel as faulted before calling g20a_channel_abort, to keep the semantics the same as the native driver. Bug 1653186 Change-Id: I0cb8ce7bad22a4d508eade6ff63a412296a02fc9 Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/811885 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/817021 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/fifo_vgpu.c')
-rw-r--r--drivers/gpu/nvgpu/vgpu/fifo_vgpu.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
index 84bb3646..a2ecd864 100644
--- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
@@ -541,7 +541,11 @@ static void vgpu_fifo_set_ctx_mmu_error(struct gk20a *g,
541int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info) 541int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info)
542{ 542{
543 struct fifo_gk20a *f = &g->fifo; 543 struct fifo_gk20a *f = &g->fifo;
544 struct channel_gk20a *ch = &f->channel[info->chid]; 544 struct channel_gk20a *ch = gk20a_channel_get(&f->channel[info->chid]);
545
546 gk20a_dbg_fn("");
547 if (!ch)
548 return 0;
545 549
546 gk20a_err(dev_from_gk20a(g), "fifo intr (%d) on ch %u", 550 gk20a_err(dev_from_gk20a(g), "fifo intr (%d) on ch %u",
547 info->type, info->chid); 551 info->type, info->chid);
@@ -555,14 +559,15 @@ int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info)
555 NVGPU_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT); 559 NVGPU_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT);
556 break; 560 break;
557 case TEGRA_VGPU_FIFO_INTR_MMU_FAULT: 561 case TEGRA_VGPU_FIFO_INTR_MMU_FAULT:
558 gk20a_channel_abort(ch);
559 vgpu_fifo_set_ctx_mmu_error(g, ch); 562 vgpu_fifo_set_ctx_mmu_error(g, ch);
563 gk20a_channel_abort(ch);
560 break; 564 break;
561 default: 565 default:
562 WARN_ON(1); 566 WARN_ON(1);
563 break; 567 break;
564 } 568 }
565 569
570 gk20a_channel_put(ch);
566 return 0; 571 return 0;
567} 572}
568 573