diff options
author | Thomas Fleury <tfleury@nvidia.com> | 2017-04-19 19:47:13 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-05-24 07:55:36 -0400 |
commit | b03afb6d5c4bbca5a26cc95027491c816e5e1f6d (patch) | |
tree | b59ae1b881877cf52ca921a5bf9d884f78fac648 /drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | |
parent | a823c72219d3bb96bc9489e84b64e0038e7119d7 (diff) |
gpu: nvgpu: add ioctls to get current timeslice
Add the following ioctls
- NVGPU_CHANNEL_IOCTL_GET_TIMESLICE for channel timeslice in us
- NVGPU_TSG_IOCTL_GET_TIMESLICE for TSG timeslice in us
If timeslice has not been set explicitly, ioctl returns the
default timeslice that will be used when programming the runlist
entry.
Bug 1883271
Change-Id: Ib18fdd836323b1a2d4efceb1e27d07713bd6fca5
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1469040
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/fifo_vgpu.c')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index 309a395a..28514386 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | |||
@@ -655,8 +655,11 @@ static int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice) | |||
655 | p->handle = ch->virt_ctx; | 655 | p->handle = ch->virt_ctx; |
656 | p->timeslice_us = timeslice; | 656 | p->timeslice_us = timeslice; |
657 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | 657 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); |
658 | WARN_ON(err || msg.ret); | 658 | err = err ? err : msg.ret; |
659 | return err ? err : msg.ret; | 659 | WARN_ON(err); |
660 | if (!err) | ||
661 | ch->timeslice_us = p->timeslice_us; | ||
662 | return err; | ||
660 | } | 663 | } |
661 | 664 | ||
662 | static int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch, | 665 | static int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch, |
@@ -776,6 +779,13 @@ int vgpu_fifo_nonstall_isr(struct gk20a *g, | |||
776 | return 0; | 779 | return 0; |
777 | } | 780 | } |
778 | 781 | ||
782 | u32 vgpu_fifo_default_timeslice_us(struct gk20a *g) | ||
783 | { | ||
784 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
785 | |||
786 | return priv->constants.default_timeslice_us; | ||
787 | } | ||
788 | |||
779 | void vgpu_init_fifo_ops(struct gpu_ops *gops) | 789 | void vgpu_init_fifo_ops(struct gpu_ops *gops) |
780 | { | 790 | { |
781 | gops->fifo.bind_channel = vgpu_channel_bind; | 791 | gops->fifo.bind_channel = vgpu_channel_bind; |
@@ -794,4 +804,5 @@ void vgpu_init_fifo_ops(struct gpu_ops *gops) | |||
794 | gops->fifo.channel_set_timeslice = vgpu_channel_set_timeslice; | 804 | gops->fifo.channel_set_timeslice = vgpu_channel_set_timeslice; |
795 | gops->fifo.force_reset_ch = vgpu_fifo_force_reset_ch; | 805 | gops->fifo.force_reset_ch = vgpu_fifo_force_reset_ch; |
796 | gops->fifo.init_engine_info = vgpu_fifo_init_engine_info; | 806 | gops->fifo.init_engine_info = vgpu_fifo_init_engine_info; |
807 | gops->fifo.default_timeslice_us = vgpu_fifo_default_timeslice_us; | ||
797 | } | 808 | } |