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author | Richard Zhao <rizhao@nvidia.com> | 2016-07-22 16:55:36 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2016-08-15 14:41:18 -0400 |
commit | 9730a93d8a44d767786ba34ffc68ef28c8e95b96 (patch) | |
tree | bd1abad55b68b57c10793b5fe1fa0b853e30f8bf /drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | |
parent | e1438818b90c5b0d73aae800b12bd6b36aec5142 (diff) |
gpu: nvgpu: vgpu: add cmd to get RM server constants
Moving getting constant attributes into one cmd which will be
called only once.
This patch adds basic infrastructure and gpu arch info, max_freq
and num_channels support.
JIRA VFND-2103
Change-Id: I100599b49f29c99966f9e90ea381b1f3c09177a3
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1189832
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/fifo_vgpu.c')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index baab42c8..9a8c319b 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | |||
@@ -237,6 +237,7 @@ static int vgpu_init_fifo_setup_sw(struct gk20a *g) | |||
237 | { | 237 | { |
238 | struct fifo_gk20a *f = &g->fifo; | 238 | struct fifo_gk20a *f = &g->fifo; |
239 | struct device *d = dev_from_gk20a(g); | 239 | struct device *d = dev_from_gk20a(g); |
240 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
240 | int chid, err = 0; | 241 | int chid, err = 0; |
241 | 242 | ||
242 | gk20a_dbg_fn(""); | 243 | gk20a_dbg_fn(""); |
@@ -247,13 +248,7 @@ static int vgpu_init_fifo_setup_sw(struct gk20a *g) | |||
247 | } | 248 | } |
248 | 249 | ||
249 | f->g = g; | 250 | f->g = g; |
250 | 251 | f->num_channels = priv->constants.num_channels; | |
251 | err = vgpu_get_attribute(vgpu_get_handle(g), | ||
252 | TEGRA_VGPU_ATTRIB_NUM_CHANNELS, | ||
253 | &f->num_channels); | ||
254 | if (err) | ||
255 | return -ENXIO; | ||
256 | |||
257 | f->max_engines = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES); | 252 | f->max_engines = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES); |
258 | 253 | ||
259 | f->userd_entry_size = 1 << ram_userd_base_shift_v(); | 254 | f->userd_entry_size = 1 << ram_userd_base_shift_v(); |