diff options
author | Aingara Paramakuru <aparamakuru@nvidia.com> | 2016-03-04 10:15:08 -0500 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-03-23 14:04:19 -0400 |
commit | 7d45a7361d104674d921dffed0f7051b0aaf1059 (patch) | |
tree | 555a79b7896a0bf30d6146f281dadfd6d3c5812e /drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | |
parent | 6e946ad3a3cf1b189d5d7705427de4d607de7f3b (diff) |
gpu: nvgpu: vgpu: add channel interleave support
Update vgpu back-end to send channel interleave request
to server.
JIRA VFND-1313
Bug 1729664
Change-Id: I2433aef485135ae9222dec238e25aedc19257744
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/1028976
(cherry picked from commit df3c5dc410839d126cc0574064d23e58102689b8)
Reviewed-on: http://git-master/r/1026049
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/fifo_vgpu.c')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 31 |
1 files changed, 30 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index b4bb7f38..a7e9eed8 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | |||
@@ -541,6 +541,35 @@ static int vgpu_channel_set_priority(struct channel_gk20a *ch, u32 priority) | |||
541 | return err ? err : msg.ret; | 541 | return err ? err : msg.ret; |
542 | } | 542 | } |
543 | 543 | ||
544 | static int vgpu_fifo_set_runlist_interleave(struct gk20a *g, | ||
545 | u32 id, | ||
546 | bool is_tsg, | ||
547 | u32 runlist_id, | ||
548 | u32 new_level) | ||
549 | { | ||
550 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); | ||
551 | struct tegra_vgpu_cmd_msg msg; | ||
552 | struct tegra_vgpu_channel_runlist_interleave_params *p = | ||
553 | &msg.params.channel_interleave; | ||
554 | struct channel_gk20a *ch; | ||
555 | int err; | ||
556 | |||
557 | gk20a_dbg_fn(""); | ||
558 | |||
559 | /* FIXME: add support for TSGs */ | ||
560 | if (is_tsg) | ||
561 | return -ENOSYS; | ||
562 | |||
563 | ch = &g->fifo.channel[id]; | ||
564 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE; | ||
565 | msg.handle = platform->virt_handle; | ||
566 | p->handle = ch->virt_ctx; | ||
567 | p->level = new_level; | ||
568 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
569 | WARN_ON(err || msg.ret); | ||
570 | return err ? err : msg.ret; | ||
571 | } | ||
572 | |||
544 | static void vgpu_fifo_set_ctx_mmu_error(struct gk20a *g, | 573 | static void vgpu_fifo_set_ctx_mmu_error(struct gk20a *g, |
545 | struct channel_gk20a *ch) | 574 | struct channel_gk20a *ch) |
546 | { | 575 | { |
@@ -626,5 +655,5 @@ void vgpu_init_fifo_ops(struct gpu_ops *gops) | |||
626 | gops->fifo.update_runlist = vgpu_fifo_update_runlist; | 655 | gops->fifo.update_runlist = vgpu_fifo_update_runlist; |
627 | gops->fifo.wait_engine_idle = vgpu_fifo_wait_engine_idle; | 656 | gops->fifo.wait_engine_idle = vgpu_fifo_wait_engine_idle; |
628 | gops->fifo.channel_set_priority = vgpu_channel_set_priority; | 657 | gops->fifo.channel_set_priority = vgpu_channel_set_priority; |
658 | gops->fifo.set_runlist_interleave = vgpu_fifo_set_runlist_interleave; | ||
629 | } | 659 | } |
630 | |||