diff options
author | Thomas Fleury <tfleury@nvidia.com> | 2017-01-25 19:59:31 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-03-09 13:44:55 -0500 |
commit | 6c35cebdcb2d14741385cfe051577882a806cdb8 (patch) | |
tree | 80c0e8f0519dc253839a1aa7c8fe6e7da7ad336a /drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | |
parent | bc47d822298b9f3b2f93a384a7780a3763fee495 (diff) |
gpu: nvgpu: vgpu: suspend/resume contexts
Add ability to suspend/resume contexts for a debug session
(NVGPU_DBG_GPU_IOCTL_SUSPEND_RESUME_CONTEXTS), in virtualized
case:
- added hal function to resume contexts.
- added vgpu support for suspend contexts, i.e. build a list
of channel ids, and send TEGRA_VGPU_CMD_SUSPEND_CONTEXTS
- added vgpu support for resume contexts, i.e. build a list
of channel ids, and send TEGRA_VGPU_CMD_RESUME_CONTEXTS
Bug 1791111
Change-Id: Icc1c00d94a94dab6384ac263fb811c00fa4b07bf
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1294761
(cherry picked from commit d17a38eda312ffa92ce92e5bafc30727a8b76c4e)
Reviewed-on: http://git-master/r/1299059
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Cory Perry <cperry@nvidia.com>
Tested-by: Cory Perry <cperry@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/fifo_vgpu.c')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index 027a92fc..0655ea15 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | |||
@@ -405,6 +405,7 @@ int vgpu_init_fifo_support(struct gk20a *g) | |||
405 | static int vgpu_fifo_preempt_channel(struct gk20a *g, u32 hw_chid) | 405 | static int vgpu_fifo_preempt_channel(struct gk20a *g, u32 hw_chid) |
406 | { | 406 | { |
407 | struct fifo_gk20a *f = &g->fifo; | 407 | struct fifo_gk20a *f = &g->fifo; |
408 | struct channel_gk20a *ch = &f->channel[hw_chid]; | ||
408 | struct tegra_vgpu_cmd_msg msg; | 409 | struct tegra_vgpu_cmd_msg msg; |
409 | struct tegra_vgpu_channel_config_params *p = | 410 | struct tegra_vgpu_channel_config_params *p = |
410 | &msg.params.channel_config; | 411 | &msg.params.channel_config; |
@@ -412,9 +413,12 @@ static int vgpu_fifo_preempt_channel(struct gk20a *g, u32 hw_chid) | |||
412 | 413 | ||
413 | gk20a_dbg_fn(""); | 414 | gk20a_dbg_fn(""); |
414 | 415 | ||
416 | if (!atomic_read(&ch->bound)) | ||
417 | return 0; | ||
418 | |||
415 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_PREEMPT; | 419 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_PREEMPT; |
416 | msg.handle = vgpu_get_handle(g); | 420 | msg.handle = vgpu_get_handle(g); |
417 | p->handle = f->channel[hw_chid].virt_ctx; | 421 | p->handle = ch->virt_ctx; |
418 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | 422 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); |
419 | 423 | ||
420 | if (err || msg.ret) { | 424 | if (err || msg.ret) { |