gpu: nvgpu: use full system barrier in BAR1 test

BAR1 test could occasionally fail when doing CPU write through userd
then reading back through BAR1. This is because nvgpu_smp_mb() only
guarantees ordering between cores.
Replaced with nvgpu_mb() to ensure the write will be visible to all
bus masters in the system.

JIRA EVLR-1959
Bug 200352099

Change-Id: Id002e73d135e0805fca2f153a6de77e210a7b226
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1582928
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
index eac720ca..2874e256 100644
--- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
@@ -397,7 +397,7 @@ int vgpu_init_fifo_setup_hw(struct gk20a *g)
                 v = gk20a_bar1_readl(g, bar1_vaddr);
 
                 *cpu_vaddr = v1;
-                nvgpu_smp_mb();
+                nvgpu_mb();
 
                 if (v1 != gk20a_bar1_readl(g, bar1_vaddr)) {
                         nvgpu_err(g, "bar1 broken @ gk20a!");