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authorRichard Zhao <rizhao@nvidia.com>2017-08-08 18:45:33 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-08-28 22:34:22 -0400
commit0e0767672ae7e66d0ec249b8847f36c685fe995e (patch)
tree79a917b0200c85307475be9bdf59dedfbd56a30e /drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
parent6365040db35fd01c8ebff39bd9dbc6c73c48fb17 (diff)
gpu: nvgpu: vgpu: get engines info from RM server
- get engines info from constants - remove according HAL from gp10b vgpu Jira VFND-3797 Change-Id: If010e59c358ab0519cb0d8d6211c0bcc20fc3723 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1536179 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/fifo_vgpu.c')
-rw-r--r--drivers/gpu/nvgpu/vgpu/fifo_vgpu.c45
1 files changed, 30 insertions, 15 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
index 3f03e25a..252b4e43 100644
--- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
@@ -163,27 +163,42 @@ static int vgpu_channel_setup_ramfc(struct channel_gk20a *ch, u64 gpfifo_base,
163 163
164static int vgpu_fifo_init_engine_info(struct fifo_gk20a *f) 164static int vgpu_fifo_init_engine_info(struct fifo_gk20a *f)
165{ 165{
166 struct fifo_engine_info_gk20a *gr_info; 166 struct vgpu_priv_data *priv = vgpu_get_priv_data(f->g);
167 struct fifo_engine_info_gk20a *ce_info; 167 struct tegra_vgpu_engines_info *engines = &priv->constants.engines_info;
168 const u32 gr_sw_id = ENGINE_GR_GK20A; 168 u32 i;
169 const u32 ce_sw_id = ENGINE_GRCE_GK20A;
170 169
171 gk20a_dbg_fn(""); 170 gk20a_dbg_fn("");
172 171
173 f->num_engines = 2; 172 if (engines->num_engines > TEGRA_VGPU_MAX_ENGINES) {
173 nvgpu_err(f->g, "num_engines %d larger than max %d",
174 engines->num_engines, TEGRA_VGPU_MAX_ENGINES);
175 return -EINVAL;
176 }
177
178 f->num_engines = engines->num_engines;
179 for (i = 0; i < f->num_engines; i++) {
180 struct fifo_engine_info_gk20a *info =
181 &f->engine_info[engines->info[i].engine_id];
174 182
175 gr_info = &f->engine_info[0]; 183 if (engines->info[i].engine_id >= f->max_engines) {
184 nvgpu_err(f->g, "engine id %d larger than max %d",
185 engines->info[i].engine_id,
186 f->max_engines);
187 return -EINVAL;
188 }
176 189
177 /* FIXME: retrieve this from server */ 190 info->intr_mask = engines->info[i].intr_mask;
178 gr_info->runlist_id = 0; 191 info->reset_mask = engines->info[i].reset_mask;
179 gr_info->engine_enum = gr_sw_id; 192 info->runlist_id = engines->info[i].runlist_id;
180 f->active_engines_list[0] = 0; 193 info->pbdma_id = engines->info[i].pbdma_id;
194 info->inst_id = engines->info[i].inst_id;
195 info->pri_base = engines->info[i].pri_base;
196 info->engine_enum = engines->info[i].engine_enum;
197 info->fault_id = engines->info[i].fault_id;
198 f->active_engines_list[i] = engines->info[i].engine_id;
199 }
181 200
182 ce_info = &f->engine_info[1]; 201 gk20a_dbg_fn("done");
183 ce_info->runlist_id = 0;
184 ce_info->inst_id = 2;
185 ce_info->engine_enum = ce_sw_id;
186 f->active_engines_list[1] = 1;
187 202
188 return 0; 203 return 0;
189} 204}