summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/vgpu/clk_vgpu.c
diff options
context:
space:
mode:
authorDeepak Nibade <dnibade@nvidia.com>2017-11-14 09:43:28 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-11-17 11:27:19 -0500
commitb42fb7ba26b565f93118fbdd9e17b42ee6144c5e (patch)
tree26e2d919f019d15b51bba4d7b5c938f77ad5cff5 /drivers/gpu/nvgpu/vgpu/clk_vgpu.c
parentb7cc3a2aa6c92a09eed43513287c9062f22ad127 (diff)
gpu: nvgpu: move vgpu code to linux
Most of VGPU code is linux specific but lies in common code So until VGPU code is properly abstracted and made os-independent, move all of VGPU code to linux specific directory Handle corresponding Makefile changes Update all #includes to reflect new paths Add GPL license to newly added linux files Jira NVGPU-387 Change-Id: Ic133e4c80e570bcc273f0dacf45283fefd678923 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1599472 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/clk_vgpu.c')
-rw-r--r--drivers/gpu/nvgpu/vgpu/clk_vgpu.c170
1 files changed, 0 insertions, 170 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/clk_vgpu.c b/drivers/gpu/nvgpu/vgpu/clk_vgpu.c
deleted file mode 100644
index e4ad8f68..00000000
--- a/drivers/gpu/nvgpu/vgpu/clk_vgpu.c
+++ /dev/null
@@ -1,170 +0,0 @@
1/*
2 * Virtualized GPU Clock Interface
3 *
4 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include "vgpu/vgpu.h"
26#include "vgpu/clk_vgpu.h"
27
28static unsigned long
29vgpu_freq_table[TEGRA_VGPU_GPU_FREQ_TABLE_SIZE];
30
31static unsigned long vgpu_clk_get_rate(struct gk20a *g, u32 api_domain)
32{
33 struct tegra_vgpu_cmd_msg msg = {};
34 struct tegra_vgpu_gpu_clk_rate_params *p = &msg.params.gpu_clk_rate;
35 int err;
36 unsigned long ret = 0;
37
38 gk20a_dbg_fn("");
39
40 switch (api_domain) {
41 case CTRL_CLK_DOMAIN_GPCCLK:
42 msg.cmd = TEGRA_VGPU_CMD_GET_GPU_CLK_RATE;
43 msg.handle = vgpu_get_handle(g);
44 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
45 err = err ? err : msg.ret;
46 if (err)
47 nvgpu_err(g, "%s failed - %d", __func__, err);
48 else
49 /* return frequency in Hz */
50 ret = p->rate * 1000;
51 break;
52 case CTRL_CLK_DOMAIN_PWRCLK:
53 nvgpu_err(g, "unsupported clock: %u", api_domain);
54 break;
55 default:
56 nvgpu_err(g, "unknown clock: %u", api_domain);
57 break;
58 }
59
60 return ret;
61}
62
63static int vgpu_clk_set_rate(struct gk20a *g,
64 u32 api_domain, unsigned long rate)
65{
66 struct tegra_vgpu_cmd_msg msg = {};
67 struct tegra_vgpu_gpu_clk_rate_params *p = &msg.params.gpu_clk_rate;
68 int err = -EINVAL;
69
70 gk20a_dbg_fn("");
71
72 switch (api_domain) {
73 case CTRL_CLK_DOMAIN_GPCCLK:
74 msg.cmd = TEGRA_VGPU_CMD_SET_GPU_CLK_RATE;
75 msg.handle = vgpu_get_handle(g);
76
77 /* server dvfs framework requires frequency in kHz */
78 p->rate = (u32)(rate / 1000);
79 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
80 err = err ? err : msg.ret;
81 if (err)
82 nvgpu_err(g, "%s failed - %d", __func__, err);
83 break;
84 case CTRL_CLK_DOMAIN_PWRCLK:
85 nvgpu_err(g, "unsupported clock: %u", api_domain);
86 break;
87 default:
88 nvgpu_err(g, "unknown clock: %u", api_domain);
89 break;
90 }
91
92 return err;
93}
94
95static unsigned long vgpu_clk_get_maxrate(struct gk20a *g, u32 api_domain)
96{
97 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
98
99 return priv->constants.max_freq;
100}
101
102void vgpu_init_clk_support(struct gk20a *g)
103{
104 g->ops.clk.get_rate = vgpu_clk_get_rate;
105 g->ops.clk.set_rate = vgpu_clk_set_rate;
106 g->ops.clk.get_maxrate = vgpu_clk_get_maxrate;
107}
108
109long vgpu_clk_round_rate(struct device *dev, unsigned long rate)
110{
111 /* server will handle frequency rounding */
112 return rate;
113}
114
115int vgpu_clk_get_freqs(struct device *dev,
116 unsigned long **freqs, int *num_freqs)
117{
118 struct gk20a_platform *platform = gk20a_get_platform(dev);
119 struct gk20a *g = platform->g;
120 struct tegra_vgpu_cmd_msg msg = {};
121 struct tegra_vgpu_get_gpu_freq_table_params *p =
122 &msg.params.get_gpu_freq_table;
123 unsigned int i;
124 int err;
125
126 gk20a_dbg_fn("");
127
128 msg.cmd = TEGRA_VGPU_CMD_GET_GPU_FREQ_TABLE;
129 msg.handle = vgpu_get_handle(g);
130
131 p->num_freqs = TEGRA_VGPU_GPU_FREQ_TABLE_SIZE;
132 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
133 err = err ? err : msg.ret;
134 if (err) {
135 nvgpu_err(g, "%s failed - %d", __func__, err);
136 return err;
137 }
138
139 /* return frequency in Hz */
140 for (i = 0; i < p->num_freqs; i++)
141 vgpu_freq_table[i] = p->freqs[i] * 1000;
142
143 *freqs = vgpu_freq_table;
144 *num_freqs = p->num_freqs;
145
146 return 0;
147}
148
149int vgpu_clk_cap_rate(struct device *dev, unsigned long rate)
150{
151 struct gk20a_platform *platform = gk20a_get_platform(dev);
152 struct gk20a *g = platform->g;
153 struct tegra_vgpu_cmd_msg msg = {};
154 struct tegra_vgpu_gpu_clk_rate_params *p = &msg.params.gpu_clk_rate;
155 int err = 0;
156
157 gk20a_dbg_fn("");
158
159 msg.cmd = TEGRA_VGPU_CMD_CAP_GPU_CLK_RATE;
160 msg.handle = vgpu_get_handle(g);
161 p->rate = (u32)rate;
162 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
163 err = err ? err : msg.ret;
164 if (err) {
165 nvgpu_err(g, "%s failed - %d", __func__, err);
166 return err;
167 }
168
169 return 0;
170}
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-04 22:10:53 -0400