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authorSachit Kadle <skadle@nvidia.com>2017-01-09 20:34:14 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-06-19 19:36:26 -0400
commit4d8895276003edf0183c94f3e2f5de378bf9d345 (patch)
tree8093dd0531718b05f8796a226c0d3f747d2289c3 /drivers/gpu/nvgpu/vgpu/clk_vgpu.c
parentb3a7c2b305ec6f895dc236f0c5f163bd4cbeb248 (diff)
gpu: nvgpu: vgpu: add freq capping support
Currently callbacks from the PM_QOS framework (for thermal events), result in a RPC call to set GPU frequency. Since the governor will now be responsible for setting desired rate, the max PM_QOS callback will now cap the possible GPU frequency w/ a new RPC call to the server. The server is responsible for setting the ultimate frequency based on the cap & desired rates. Jira VFND-3699 Change-Id: I806e309c40abc2f1381b6a23f2d898cfe26f9794 Signed-off-by: Sachit Kadle <skadle@nvidia.com> Reviewed-on: http://git-master/r/1295543 (cherry picked from commit e81693c6e087f8f10a985be83715042fc590d6db) Reviewed-on: http://git-master/r/1282467 (cherry picked from commit 7b4e0db647572e82a8d53e823c36b465781f4942) Reviewed-on: http://git-master/r/1321836 (cherry picked from commit 57dafc08a57ea768eb302bf1adb901425ce2f835) Reviewed-on: http://git-master/r/1313469 Tested-by: Aparna Das <aparnad@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/clk_vgpu.c')
-rw-r--r--drivers/gpu/nvgpu/vgpu/clk_vgpu.c23
1 files changed, 23 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/clk_vgpu.c b/drivers/gpu/nvgpu/vgpu/clk_vgpu.c
index fe5533b6..d728e02b 100644
--- a/drivers/gpu/nvgpu/vgpu/clk_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/clk_vgpu.c
@@ -128,3 +128,26 @@ int vgpu_clk_get_freqs(struct device *dev,
128 128
129 return 0; 129 return 0;
130} 130}
131
132int vgpu_clk_cap_rate(struct device *dev, unsigned long rate)
133{
134 struct gk20a_platform *platform = gk20a_get_platform(dev);
135 struct gk20a *g = platform->g;
136 struct tegra_vgpu_cmd_msg msg = {};
137 struct tegra_vgpu_gpu_clk_rate_params *p = &msg.params.gpu_clk_rate;
138 int err = 0;
139
140 gk20a_dbg_fn("");
141
142 msg.cmd = TEGRA_VGPU_CMD_CAP_GPU_CLK_RATE;
143 msg.handle = vgpu_get_handle(g);
144 p->rate = (u32)rate;
145 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
146 err = err ? err : msg.ret;
147 if (err) {
148 nvgpu_err(g, "%s failed - %d", __func__, err);
149 return err;
150 }
151
152 return 0;
153}