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| author | Deepak Nibade <dnibade@nvidia.com> | 2019-07-09 05:42:32 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2019-11-04 09:10:39 -0500 |
| commit | 0ffc5fa5e44c623b6fde3d6bed5369b9674ee089 (patch) | |
| tree | 5fcf39cd05d2128dd05837c36bdd89a24f4ac631 /drivers/gpu/nvgpu/therm/thrm.c | |
| parent | aa43252d1a60db5d317a71787e2aee3b0d7cb8a8 (diff) | |
gpu: nvgpu: add clock gating support for HSHUB
Add BLCG and SLCG clock gating support for HSHUB unit on gv11b
Register list for BLCG and SLCG is auto generated with scripts.
Add HAL operations to enable/disable HSHUB clock gating
Re-generate gv11b reglist so that all the manually commented registers
are automatically deleted. Some of the unicast registers are also
deleted. We already have corresponding broadcast registers present.
Cherry-pick/manually port from dev-main
Bug 2526212
Change-Id: I2654f158daa802bcf992e103ed4a44675aa5fd4d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2150199
(cherry picked from commit e34b6f76d38ad5641c1ed7c3a4b36752d9dd4750)
Reviewed-on: https://git-master.nvidia.com/r/2224708
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-by: Luis Dib <ldib@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/therm/thrm.c')
0 files changed, 0 insertions, 0 deletions