gpu: nvgpu: MSCG support

- update gp106 pg engine init/list/features HALs
  to support MS engine
- Added defines & interface for lpwr tables read  from vbios.
- lpwr module which reads idx/gr/ms table from vbios to
  map rppg/mscg support with respective p-state
- lpwr module public functions to control lpwr
  features enable/disable mscg/rppg & mclk-change
  request whenever change in mclk-change parameters
- lpwr public functions to know rppg/mscg support for
  requested pstate,
- added mutex t prevent PG transition while arbiter
  executes pstate transition
- nvgpu_clk_arb_get_current_pstate() of clk arbiter to
  get current pstate

JIRA DNVGPU-71

Change-Id: Ifcd640cc19ef630be1e2a9ba07ec84023d8202a0
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1247553
(cherry picked from commit 8a441dea2410e1b5196ef24e56a7768b6980e46b)
Reviewed-on: http://git-master/r/1270989
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 12 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/pstate/pstate.c b/drivers/gpu/nvgpu/pstate/pstate.c
index 2e08ef01..82e809bb 100644
--- a/drivers/gpu/nvgpu/pstate/pstate.c
+++ b/drivers/gpu/nvgpu/pstate/pstate.c
@@ -83,6 +83,10 @@ int gk20a_init_pstate_support(struct gk20a *g)
                 return err;
 
         err = clk_freq_controller_sw_setup(g);
+        if (err)
+                return err;
+
+        err = nvgpu_lpwr_pg_setup(g);
 
         return err;
 }
@@ -327,6 +331,9 @@ static int pstate_sw_setup(struct gk20a *g)
 
         gk20a_dbg_fn("");
 
+        init_waitqueue_head(&g->perf_pmu.pstatesobjs.pstate_notifier_wq);
+        mutex_init(&g->perf_pmu.pstatesobjs.pstate_mutex);
+
         err = boardobjgrpconstruct_e32(&g->perf_pmu.pstatesobjs.super);
         if (err) {
                 gk20a_err(dev_from_gk20a(g),
@@ -361,7 +368,7 @@ done:
         return err;
 }
 
-static struct pstate *pstate_find(struct gk20a *g, u32 num)
+struct pstate *pstate_find(struct gk20a *g, u32 num)
 {
         struct pstates *pstates = &(g->perf_pmu.pstatesobjs);
         struct pstate *pstate;
diff --git a/drivers/gpu/nvgpu/pstate/pstate.h b/drivers/gpu/nvgpu/pstate/pstate.h
index b6519c20..af0956e8 100644
--- a/drivers/gpu/nvgpu/pstate/pstate.h
+++ b/drivers/gpu/nvgpu/pstate/pstate.h
@@ -48,6 +48,9 @@ struct pstate {
 struct pstates {
         struct boardobjgrp_e32 super;
         u32  num_levels;
+        wait_queue_head_t pstate_notifier_wq;
+        u32 is_pstate_switch_on;
+        struct mutex pstate_mutex; /* protect is_pstate_switch_on */
 };
 
 int gk20a_init_pstate_support(struct gk20a *g);
@@ -55,5 +58,6 @@ int gk20a_init_pstate_pmu_support(struct gk20a *g);
 
 struct clk_set_info *pstate_get_clk_set_info(struct gk20a *g, u32 pstate_num,
                 enum nv_pmu_clk_clkwhich clkwhich);
+struct pstate *pstate_find(struct gk20a *g, u32 num);
 
 #endif /* __PSTATE_H__ */