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author | Thomas Fleury <tfleury@nvidia.com> | 2016-09-13 17:23:45 -0400 |
---|---|---|
committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 04:56:51 -0500 |
commit | 3d9c33c5953e383527c7e4af594adfe0c82b5788 (patch) | |
tree | 6de4ae86667c763ed0deef3add9336b570ca15ff /drivers/gpu/nvgpu/pstate/pstate.h | |
parent | c320ccfa952a2796db27d97111791bcbeff9f5c7 (diff) |
gpu: nvgpu: clk arbiter skeleton
Add clock arbiter skeleton with support of clock sessions,
notifications on clock changes, request numbering, and asynchronous
handling of clock requests. Provides minimum behaviour to allow
unit tests implementation. Actual arbitration and clock settings
will be done separately. For now, dummy arbiter keeps last
requested target mhz. Actual arbiter may move to a lockless
implementation.
Jira DNVGPU-125
Change-Id: I6a8e443fb0d15dc5f1993e7260256d71acddd106
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1223476
(cherry picked from commit cb130825d84e4124d273bd443e2b62d493377461)
Reviewed-on: http://git-master/r/1243105
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/pstate/pstate.h')
-rw-r--r-- | drivers/gpu/nvgpu/pstate/pstate.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/pstate/pstate.h b/drivers/gpu/nvgpu/pstate/pstate.h index 11fa4c77..4ae72aa9 100644 --- a/drivers/gpu/nvgpu/pstate/pstate.h +++ b/drivers/gpu/nvgpu/pstate/pstate.h | |||
@@ -20,6 +20,10 @@ | |||
20 | 20 | ||
21 | #define CTRL_PERF_PSTATE_TYPE_3X 0x3 | 21 | #define CTRL_PERF_PSTATE_TYPE_3X 0x3 |
22 | 22 | ||
23 | #define CTRL_PERF_PSTATE_P0 0 | ||
24 | #define CTRL_PERF_PSTATE_P5 5 | ||
25 | #define CTRL_PERF_PSTATE_P8 8 | ||
26 | |||
23 | #define CLK_SET_INFO_MAX_SIZE (32) | 27 | #define CLK_SET_INFO_MAX_SIZE (32) |
24 | 28 | ||
25 | struct clk_set_info { | 29 | struct clk_set_info { |
@@ -30,7 +34,7 @@ struct clk_set_info { | |||
30 | }; | 34 | }; |
31 | 35 | ||
32 | struct clk_set_info_list { | 36 | struct clk_set_info_list { |
33 | u32 clksetinfolistsize; | 37 | u32 num_info; |
34 | struct clk_set_info clksetinfo[CLK_SET_INFO_MAX_SIZE]; | 38 | struct clk_set_info clksetinfo[CLK_SET_INFO_MAX_SIZE]; |
35 | }; | 39 | }; |
36 | 40 | ||
@@ -48,4 +52,7 @@ struct pstates { | |||
48 | int gk20a_init_pstate_support(struct gk20a *g); | 52 | int gk20a_init_pstate_support(struct gk20a *g); |
49 | int gk20a_init_pstate_pmu_support(struct gk20a *g); | 53 | int gk20a_init_pstate_pmu_support(struct gk20a *g); |
50 | 54 | ||
55 | struct clk_set_info *pstate_get_clk_set_info(struct gk20a *g, u32 pstate_num, | ||
56 | enum nv_pmu_clk_clkwhich clkwhich); | ||
57 | |||
51 | #endif /* __PSTATE_H__ */ | 58 | #endif /* __PSTATE_H__ */ |