diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2018-04-18 22:39:46 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-05-09 21:26:04 -0400 |
commit | dd739fcb039d51606e9a5454ec0aab17bcb01965 (patch) | |
tree | 806ba8575d146367ad1be00086ca0cdae35a6b28 /drivers/gpu/nvgpu/pstate/pstate.c | |
parent | 7e66f2a63d4855e763fa768047dfc32f6f96b771 (diff) |
gpu: nvgpu: Remove gk20a_dbg* functions
Switch all logging to nvgpu_log*(). gk20a_dbg* macros are
intentionally left there because of use from other repositories.
Because the new functions do not work without a pointer to struct
gk20a, and piping it just for logging is excessive, some log messages
are deleted.
Change-Id: I00e22e75fe4596a330bb0282ab4774b3639ee31e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1704148
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/pstate/pstate.c')
-rw-r--r-- | drivers/gpu/nvgpu/pstate/pstate.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/pstate/pstate.c b/drivers/gpu/nvgpu/pstate/pstate.c index c3f34027..e61ec0f8 100644 --- a/drivers/gpu/nvgpu/pstate/pstate.c +++ b/drivers/gpu/nvgpu/pstate/pstate.c | |||
@@ -46,7 +46,7 @@ int gk20a_init_pstate_support(struct gk20a *g) | |||
46 | { | 46 | { |
47 | u32 err; | 47 | u32 err; |
48 | 48 | ||
49 | gk20a_dbg_fn(""); | 49 | nvgpu_log_fn(g, " "); |
50 | 50 | ||
51 | err = volt_rail_sw_setup(g); | 51 | err = volt_rail_sw_setup(g); |
52 | if (err) | 52 | if (err) |
@@ -114,7 +114,7 @@ int gk20a_init_pstate_pmu_support(struct gk20a *g) | |||
114 | { | 114 | { |
115 | u32 err; | 115 | u32 err; |
116 | 116 | ||
117 | gk20a_dbg_fn(""); | 117 | nvgpu_log_fn(g, " "); |
118 | 118 | ||
119 | if (g->ops.clk.mclk_init) { | 119 | if (g->ops.clk.mclk_init) { |
120 | err = g->ops.clk.mclk_init(g); | 120 | err = g->ops.clk.mclk_init(g); |
@@ -269,7 +269,7 @@ static int parse_pstate_entry_5x(struct gk20a *g, | |||
269 | pstate->clklist.num_info = hdr->clock_entry_count; | 269 | pstate->clklist.num_info = hdr->clock_entry_count; |
270 | pstate->lpwr_entry_idx = entry->lpwr_entry_idx; | 270 | pstate->lpwr_entry_idx = entry->lpwr_entry_idx; |
271 | 271 | ||
272 | gk20a_dbg_info("pstate P%u", pstate->num); | 272 | nvgpu_log_info(g, "pstate P%u", pstate->num); |
273 | 273 | ||
274 | for (clkidx = 0; clkidx < hdr->clock_entry_count; clkidx++) { | 274 | for (clkidx = 0; clkidx < hdr->clock_entry_count; clkidx++) { |
275 | struct clk_set_info *pclksetinfo; | 275 | struct clk_set_info *pclksetinfo; |
@@ -293,7 +293,7 @@ static int parse_pstate_entry_5x(struct gk20a *g, | |||
293 | BIOS_GET_FIELD(clk_entry->param1, | 293 | BIOS_GET_FIELD(clk_entry->param1, |
294 | VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MAX_FREQ_MHZ); | 294 | VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MAX_FREQ_MHZ); |
295 | 295 | ||
296 | gk20a_dbg_info( | 296 | nvgpu_log_info(g, |
297 | "clk_domain=%u nominal_mhz=%u min_mhz=%u max_mhz=%u", | 297 | "clk_domain=%u nominal_mhz=%u min_mhz=%u max_mhz=%u", |
298 | pclksetinfo->clkwhich, pclksetinfo->nominal_mhz, | 298 | pclksetinfo->clkwhich, pclksetinfo->nominal_mhz, |
299 | pclksetinfo->min_mhz, pclksetinfo->max_mhz); | 299 | pclksetinfo->min_mhz, pclksetinfo->max_mhz); |
@@ -355,7 +355,7 @@ static int pstate_sw_setup(struct gk20a *g) | |||
355 | struct vbios_pstate_header_5x *hdr = NULL; | 355 | struct vbios_pstate_header_5x *hdr = NULL; |
356 | int err = 0; | 356 | int err = 0; |
357 | 357 | ||
358 | gk20a_dbg_fn(""); | 358 | nvgpu_log_fn(g, " "); |
359 | 359 | ||
360 | nvgpu_cond_init(&g->perf_pmu.pstatesobjs.pstate_notifier_wq); | 360 | nvgpu_cond_init(&g->perf_pmu.pstatesobjs.pstate_notifier_wq); |
361 | 361 | ||
@@ -401,11 +401,11 @@ struct pstate *pstate_find(struct gk20a *g, u32 num) | |||
401 | struct pstate *pstate; | 401 | struct pstate *pstate; |
402 | u8 i; | 402 | u8 i; |
403 | 403 | ||
404 | gk20a_dbg_info("pstates = %p", pstates); | 404 | nvgpu_log_info(g, "pstates = %p", pstates); |
405 | 405 | ||
406 | BOARDOBJGRP_FOR_EACH(&pstates->super.super, | 406 | BOARDOBJGRP_FOR_EACH(&pstates->super.super, |
407 | struct pstate *, pstate, i) { | 407 | struct pstate *, pstate, i) { |
408 | gk20a_dbg_info("pstate=%p num=%u (looking for num=%u)", | 408 | nvgpu_log_info(g, "pstate=%p num=%u (looking for num=%u)", |
409 | pstate, pstate->num, num); | 409 | pstate, pstate->num, num); |
410 | if (pstate->num == num) | 410 | if (pstate->num == num) |
411 | return pstate; | 411 | return pstate; |
@@ -420,7 +420,7 @@ struct clk_set_info *pstate_get_clk_set_info(struct gk20a *g, | |||
420 | struct clk_set_info *info; | 420 | struct clk_set_info *info; |
421 | u32 clkidx; | 421 | u32 clkidx; |
422 | 422 | ||
423 | gk20a_dbg_info("pstate = %p", pstate); | 423 | nvgpu_log_info(g, "pstate = %p", pstate); |
424 | 424 | ||
425 | if (!pstate) | 425 | if (!pstate) |
426 | return NULL; | 426 | return NULL; |