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authorMahantesh Kumbar <mkumbar@nvidia.com>2018-06-20 03:14:04 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-07-05 09:43:44 -0400
commitbc05e0e0e5b7d00761472252e9f8c12886539746 (patch)
tree3e44315e10bd844d417217a1da18e51771bf5e15 /drivers/gpu/nvgpu/pstate/pstate.c
parent84db72a21ce4076a66acbb936b5a6dabf39c7ee2 (diff)
gpu: nvgpu: SEC2 reset using common falcon HAL
-Do sec2 reset using common falcon HAL nvgpu_flcn_reset() by passing sec2_flcn struct which holds base address of SEC2 falcon as per chip specific. JIRA NVGPUT-111 Change-Id: I2b95262a93644bbefed5b6c46dc73200afd97730 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1755617 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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