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authorVaikundanathan S <vaikuns@nvidia.com>2018-08-28 02:28:25 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-20 13:50:53 -0400
commitae809fddbe90bcec0d48e1213fa36cc5ba76550d (patch)
treebbafc71a543abf4b02e76290d058719f27f5f3b8 /drivers/gpu/nvgpu/pstate/pstate.c
parent85c323c3e89d6e1b624b839c3325ae072952e545 (diff)
gpu:nvgpu: Add GV10x perf event
In case of VFE update, schedule work to set P0 clocks. Added function nvgpu_clk_set_fll_clk_gv10x to update P0 clocks on perf event. Fixed MISRA issues caused by this excluding external functions and MACROs Bug 2331655 Change-Id: Id96c473092ee7f0b651413aefdd4b6f2f59e0b12 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1808014 Reviewed-on: https://git-master.nvidia.com/r/1813881 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/pstate/pstate.c')
-rw-r--r--drivers/gpu/nvgpu/pstate/pstate.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/pstate/pstate.c b/drivers/gpu/nvgpu/pstate/pstate.c
index 80f3edb6..0e7404cb 100644
--- a/drivers/gpu/nvgpu/pstate/pstate.c
+++ b/drivers/gpu/nvgpu/pstate/pstate.c
@@ -222,7 +222,7 @@ int gk20a_init_pstate_pmu_support(struct gk20a *g)
222 return err; 222 return err;
223 } 223 }
224 224
225 err = g->ops.pmu_ver.clk.perf_pmu_vfe_load(g); 225 err = g->ops.clk.perf_pmu_vfe_load(g);
226 if (err) { 226 if (err) {
227 return err; 227 return err;
228 } 228 }