diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 05:01:00 -0500 |
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committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 05:35:06 -0500 |
commit | 7a81883a0d70c3a43ad2841ac235f6dc344c60fb (patch) | |
tree | 92923d2efccf90d1961071fa9acde59178a0d688 /drivers/gpu/nvgpu/pmuif | |
parent | 505b442551a2e27aa3bc9e608c5a2bc9fccecbc4 (diff) | |
parent | 2aa3c85f8e82b3c07c39e677663abd3687c1822a (diff) |
Merge remote-tracking branch 'remotes/origin/dev/merge-nvgpu-t18x-into-nvgpu' into dev-kernel
Merge T186 - gp10b/gp106 code into common nvgpu repo
Bug 200266498
Change-Id: Ibf100ee38010cbed85c149b69b99147256f9a005
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/pmuif')
-rw-r--r-- | drivers/gpu/nvgpu/pmuif/gpmuifseq.h | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifseq.h b/drivers/gpu/nvgpu/pmuif/gpmuifseq.h new file mode 100644 index 00000000..69d55490 --- /dev/null +++ b/drivers/gpu/nvgpu/pmuif/gpmuifseq.h | |||
@@ -0,0 +1,73 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef _GPMUIFSEQ_H_ | ||
14 | #define _GPMUIFSEQ_H_ | ||
15 | |||
16 | #include "gk20a/pmu_common.h" | ||
17 | |||
18 | #define PMU_UNIT_SEQ (0x02) | ||
19 | |||
20 | /*! | ||
21 | * @file gpmuifseq.h | ||
22 | * @brief PMU Command/Message Interfaces - Sequencer | ||
23 | */ | ||
24 | |||
25 | /*! | ||
26 | * Defines the identifiers various high-level types of sequencer commands. | ||
27 | * | ||
28 | * _RUN_SCRIPT @ref NV_PMU_SEQ_CMD_RUN_SCRIPT | ||
29 | */ | ||
30 | enum { | ||
31 | NV_PMU_SEQ_CMD_ID_RUN_SCRIPT = 0, | ||
32 | }; | ||
33 | |||
34 | struct nv_pmu_seq_cmd_run_script { | ||
35 | u8 cmd_type; | ||
36 | u8 pad[3]; | ||
37 | struct pmu_allocation_v3 script_alloc; | ||
38 | struct pmu_allocation_v3 reg_alloc; | ||
39 | }; | ||
40 | |||
41 | #define NV_PMU_SEQ_CMD_ALLOC_OFFSET 4 | ||
42 | |||
43 | #define NV_PMU_SEQ_MSG_ALLOC_OFFSET \ | ||
44 | (NV_PMU_SEQ_CMD_ALLOC_OFFSET + NV_PMU_CMD_ALLOC_SIZE) | ||
45 | |||
46 | struct nv_pmu_seq_cmd { | ||
47 | struct pmu_hdr hdr; | ||
48 | union { | ||
49 | u8 cmd_type; | ||
50 | struct nv_pmu_seq_cmd_run_script run_script; | ||
51 | }; | ||
52 | }; | ||
53 | |||
54 | enum { | ||
55 | NV_PMU_SEQ_MSG_ID_RUN_SCRIPT = 0, | ||
56 | }; | ||
57 | |||
58 | struct nv_pmu_seq_msg_run_script { | ||
59 | u8 msg_type; | ||
60 | u8 error_code; | ||
61 | u16 error_pc; | ||
62 | u32 timeout_stat; | ||
63 | }; | ||
64 | |||
65 | struct nv_pmu_seq_msg { | ||
66 | struct pmu_hdr hdr; | ||
67 | union { | ||
68 | u8 msg_type; | ||
69 | struct nv_pmu_seq_msg_run_script run_script; | ||
70 | }; | ||
71 | }; | ||
72 | |||
73 | #endif | ||